Data processing system emulation with microprocessor in place

Apparatus for testing a data processing system including a microprocessor, said testing occurring with said microprocessor in place in said system, said apparatus comprising:

• a support microprocessor for controlling said testing;
• a serial-to-parallel and parallel-to-serial converter connected between said support microprocessor and said system microprocessor;
• means for supplying a series of parallel level sensitive scan design test signals from said support microprocessor through the parallel-to-serial portion of said converter to supply a series of serial test signals to said system microprocessor;
• said system microprocessor having both low level and high level functions to be tested;
• additional internal logic within said system microprocessor to support said low level testing functions of said system microprocessor in response to said level sensitive scan design test signals;
• said support microprocessor providing signals for testing both said low level testing functions and said high level testing functions for testing said system microprocessor;
• and
• means for returning the serial results of said low and said high level sensitive scan design test signals from said system microprocessor through the serial-to-parallel portion of said converter to supply a series of parallel test signal results to said support microprocessor.