Packet switch with variable data transfer rate links

A packet switch with variable data transfer rate links, which forms a packet switching network of a packet switching system, comprising:

• a multi-stage structure including a plurality of unit packet switches, each of said unit packet switches including:
• connections for a plurality of incoming trunks;
• a plurality of input circuits connected to said connections for the plurality of incoming trunks, respectively, and each having a FIFO memory;
• connections for a plurality of outgoing trunks;
• a plurality of output circuits connected to said connections for the plurality of outgoing trunks, respectively, and each having a FIFO memory;
• a buffer memory which is used in common for the incoming trunks and the outgoing trunks, by writing data received from the incoming trunks and reading it out for transfer to the outgoing trunks, the FIFO memory of each of the input circuits for temporarily storing the received data from the corresponding incoming trunk, the FIFO memory of each of the output circuits for temporarily storing the data to be sent to the corresponding outgoing trunk;
• first signal lines, respectively connected to said input circuits, for providing information indicating the arrival of data at the corresponding input circuit from the incoming trunk connected thereto;
• a first arbiter, connected to said first signal lines, for detecting data-process requests from said input circuits on the basis of the information provided on said first signal lines and for effecting priority control for servicing the requests;
• second signal lines, respectively connected to said output circuits, for providing information indicating whether or not data transfer to the corresponding output circuit is possible;
• and
• a second arbiter connected to said second signal lines, for detecting data-process requests from said output circuits on the basis of the information provided on said second signal lines and for effecting priority control for servicing the requests;
• links interconnecting the respective stages of the unit packet switches, for performing asynchronous packet data transfer by handshaking;
• and
• a control circuit for controlling the data transfer by handshaking while dynamically changing the capacity of each of said links within a range in which the sum of data transfer rates of said links accommodated in each unit packet switch is smaller than the operational speed of said buffer memory in said unit packet switch.