US 4,788,670 AGranted

Clock voltage supply

AssigneeSiemens Aktiengesellschaft

InventorsHermann Hofmann, David Johnson, Werner Schirl, Hans-Peter Troendle

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Abstract

A clock voltage supply for electronic control circuits such as a computer system for generating four clock signals which are synchronous as to frequency and phase. When n=4, the clock signals are generated with the help of four PLL clocks. So that the four clock signals can continue to appear even if one of the four clocks is malfunctioning, the clock signals of the four clocks are supplied to four (3:4) voters from whose outputs the clock signals are then supplied. Since each voter circuit brings about a certain delay time, which significantly limits the frequency of the clock signals, a delay element is connected downstream to each of the voter outputs respectively. The delay time of the respective delay element, plus the delay time of the respective voter connected therewith, is an integral multiple of the period of the intended clock frequency. For PLL control, the output of each delay element gives the nominal phase position and the output of each clock gives the actual phase position.

Claims5

Dependent claims

A clock voltage supply for generating multiple parallel clock signals at a predetermined reference frequency for an electronic control circuit having N phase-controllable clocks and N voters, each phase controllable clock having an output which is connected to one input of each of N voters, wherein N is an integer greater than one and the parallel clock signals are synchronous to each other in frequency and phase, comprising:

a concatenation of a plurality of logic circuits for combining input signals and output signals in each of the voters;
means for providing a delay time for the concatenation of a plurality of logic circuits, wherein the delay time corresponds to a predetermined reference value;
at least one delay element having a first delay time, the delay element being connected downstream of one of the voters, the voter having a predetermined delay time, the predetermined delay time being the sum of the first delay time and a corresponding voter delay time, the corresponding voter delay time being equal to an integer multiple of the period of a predetermined reference frequency;
and
means for controlling the phase of the parallel clock signals utilizing a clock output signal and the output signal of the delay element associated therewith, the clock output signal being an actual phase input and the output signal being a reference phase value.

2 more elements

Dependencies are inferred from the claim text.