Semiconductor memory
AssigneeHitachi, Ltd.
InventorsMinoru Fukuda, Hideaki Takahashi, June Sugiura, Fumio Tsuchiya, Toshimasa Kihara
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Abstract
An electrically programmable read only memory is equipped with latch circuits for sequentially introducing series signals which are fed through external terminals. The converter includes sequentially operated switch elements and latch circuits in order to convert the series signals into parallel signals. The thus converted parallel signals are written simultaneously in a memory array via address decoder operated selection switch elements. According to this method, the writing operations into the memory array can be conducted at a high speed even when one writing operation is relatively long as a result of the parallel signal action.
Claims22
In a semiconductor memory, the improvement for writing information comprising:
- a memory array, having plural data lines;
- including a plurality of semiconductor nonvolatile memory cells which can be erased and electrically written into;
- external terminal means for receiving serially applied input signals to be written into the memory array;
- first common data lines;
- an external means for receiving a writing voltage;
- a plurality of writing circuits, each having a terminal coupled to said external means and having an input and an output;
- a first selector means and a second selector means;
- and
- a plurality of storage circuit means, each having an input and an output, for temporarily storing respective input signals,
- wherein said seocnd selector means seqeuntially feeds said input signals, via a plurality of signal paths, to the inputs of said plurality of storage circuit means,
- wherein said plurality of writing circuits correspond in number to said first common data lines and its outputs are coupled to said first common data lines,
- wherein said plurality of storage circuit means correspond in number to said writing circuits and its outputs are operatively connected to the inputs of said writing circuits for providing said temporarily stored signals to said writing circuits, and
- wherein said first selector means, in response to address signals, operatively connects said first common data lines to said plural data lines for writing the stored data into the memory cells, wherein said plural data lines are greater in number than said first common data lines.
In a semiconductor memory, the improvement for writing information comprising:
- a memory array having data lines, including a plurality of nonvolatile semiconductor memory cells which can be erased and electrically written into;
- external terminal means for receiving serially applied input signals or an input signal to be written into said memory array;
- converter means having an input coupled to said external terminal means and having a plurality of outputs, said converter means responding to said serially applied input signals for converting said signals into a plurality of parallel produced output signals;
- a plurality of terminals, corresponding in number to said outputs of said converter means, and coupled to said outputs of said converter means and to the data lines of said memory array;
- transmitting means having an input coupled to said external terminal means and having a plurality of outputs coupled to said terminals, said transmitting means responding to said input signal for transmitting said input signal to one of said terminals;
- and
- control means coupled to said converter means and to said transmitting means for controlling the operation of said converter means and said transmitting means.
Dependencies are inferred from the claim text.