Word line drive circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorYouichi Tobita
Life of this patent
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Abstract
In a word line drive circuit providing a word line drive signal for a random access memory, the drive signal has a smooth rising curve to attain a high data reading speed. The circuit comprises two FETs which are series connected between a terminal at which an internally boosted voltage is provided and the ground. The drive signal is provided from the junction of the two FETs. A voltage of the control signal is increased by a boosting capacitor to a level sufficient to keep the FET (connected to the boosted voltage terminal) nonconductive until production of the drive signal is desired. The resultant drive signal has an inverse phase to the phase of the control signals.
Claims11
A drive circuit comprising
- a first FET and a second FET which are connected in series and between a first power supply terminal and a second power supply terminal, a junction of said first FET and said second FET being connected to an output terminal which provides a drive signal, and said first FET having an opposite conductivity to said second FET,
- a boosting capacitor having a first electrode connected to a gate of said first FET and a second electrode connected to a first node to which a first control signal is supplied, and
- drive means which generates a second control signal and supplies said second control signal to said gate of said first FET,
- said first control signal and said second control signal having a substantially inverse phase to the phase of said drive signal.
A word line drive circuit for a random access memory to provide a drive signal having a voltage greater than a voltage V supplied from an external power supply for said circuit, said circuit comprising
- a first power supply terminal and a second power supply terminal,
- means providing said first power supply terminal with a voltage greater than the voltage supplied from an external power supply,
- a first FET and a second FET which are connected in series and between said first power supply terminal and said second power supply terminal,
- a junction of said first FET and said second FET being connected to an output terminal at which said drive signal is produced and said first FET having an opposite conductivity to said second FET,
- a boosting capacitor having a first electrode connected to a gate of said first FET and a second electrode connected to a node to which a first control signal having a substantially inverse phase to that of said drive signal is supplied, and
- drive means which supplies a second control signal to said gate of said first FET,
- said second control signal having the same phase as that of said first control signal, and a voltage of said second control signal being increased by said boosting capacitor to a level sufficient to keep said first FET nonconductive.
Dependencies are inferred from the claim text.