Semiconductor memory device using resonant-tunneling hot electron transistor

A semiconductor memory device comprising:

• a plurality of address lines;
• a plurality of write lines;
• a plurality of read lines;
• and
• a memory cell array constituted by a plurality of identical memory cells, each of said memory cells being connected to one of said address lines, one of said write lines and one of said read lines,
• each of said memory cells comprising a memory active element, a power source coupled to a base of said memory active element through a first resistor, a switching element coupled between a corresponding one of said write lines and the base of said memory active element and controlled by a signal from a corresponding one of said address lines, and a data transfer element coupled between a corresponding one of said read lines and a collector of said memory active element, said collector being coupled to the power source through a second resistor,
• said memory active element having a plurality of stable states and comprising an emitter potential barrier layer constituted by an emitter layer, a base layer and a superlattice layer formed between said emitter layer and said base layer, and a collector potential barrier layer formed between said base layer and a collector layer,
• a base-emitter voltage versus current characteristic of said memory active element having at least one differential negative resistance region,
• said data transfer element of a predetermined memory cell during a read operation of said semiconductor memory device transferring to a corresponding one of said read lines a signal corresponding to one of said plurality of stable states of said memory active element of said predetermined memory cell.