Cache memory and pre-processor
AssigneeThe Johns Hopkins University
InventorWayne I. Sternberger
Life of this patent
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Abstract
The invention relates to an apparatus for interfacing between a peripheral device and a host processor. The invented cache memory and pre-processor operates in either an acquisition mode, where it appears to be a memory dedicated to the peripheral, or in a retrieval mode, where it appears to be a memory dedicated to the host microprocessor. For example, the cache memory can be reconfigured from a 2K byte by 16-bit space during the acquisition mode to a 4K byte .times.8-bit space during the retrieval mode, wherein the high and low bytes of the previously defined 16-bit words are interleaved.
Claims13
An apparatus for interfacing between a peripheral device which outputs Q-bit data words and a host processor having an N bit data bus, wherein data are acquired from the peripheral device during an acquisition mode and retrieved from said interface apparatus during a retrieval mode, said apparatus comprising:
- a plurality of single port memories, each memory having a M byte by N bit memory space;
- a first bus transceiver means for connecting, during the acquisition mode, a different N bit portion of said Q bit data word to each of said plurality of memories;
- a second bus transceiver means for directly connecting, during the retrieval mode, the data lines of each of said plurality of memories to the host processor N bit data bus;
- a counter means for generating an incremental address each time the peripheral generates a new data word;
- an address multiplexing means, for connecting the address lines of each of said plurality of single port memories to said counter means during the acquisition mode, and for directly connecting the address lines of each of said plurality of single port memories to certain most significant bits of he host processor address bus during the retrieval mode;
- and,
- a selector means, operably connected to each of said plurality of single port memories, for alternatively enabling each of said plurality of single port memories in response to certain least significant bits of the host processors address bus during the retrieval mode.
An apparatus for interfacing between a 16-bit peripheral device and an 8-bit host processor, comprising:
- a first single port memory configured as an M byte by 8-bit memory space;
- a second single port memory configured as an M byte by 8-bit memory space;
- a first transceiver means for connecting, during the acquisition mode, the least significant 8 bits of the peripheral output to the data lines of said first single port memory and the most significant 8 bits of the peripheral output to the data lines of said second single port memory;
- a second bus transceiver means for directly connecting, during the retrieval mode, the host processor data bus to data lines of said first and second single port memory;
- a counter means for generating an incremental address each time the peripheral generates a new data word;
- an address multiplexer means for connecting the address lines of said first and second single port memory to said address means during the acquisition modes, and for directly connecting the address lines of said first and second single port memory to all but the least significant bit of the host processor address bus during the retrieval mode;
- and,
- a selector means, operably connected to said first and second single port memory, for alternatively enabling said first or second single port memory in response to the least singnificant bit of the host processor address bus during the retrieval mode.
The method of interfacing with a peripheral so as to efficiently calculate mean and standard deviation values, comprising the steps of:
- configuring a single port memory space to acquire M bit words;
- reading data from a peripheral to said memory space while a counter means triggered by the peripheral generates an address for each data word;
- comparing exponent values appearing in each data word and recording the largest;
- disconnecting the peripheral from said single port memory space;
- reconfiguring said single port memory space to deliver N bit words;
- retrieve data from said single port memory space in N bit words under direct control of the processor address line;
- retrieve the largest exponent value;
- normalize the data words to a common exponent value;
- calculate the mean value;
- rewrite normalized data words into said single port memory space;
- retrieve normalized data words from said single port memory space;
- and,
- calculate standard deviation values.
Dependencies are inferred from the claim text.