Data transfer apparatus between input/output devices and main storage with channel devices being of a concentrated type and stand-alone type

A data transfer apparatus comprising:

• a plurality of channel devices wherein each of said plurality of channel devices includes:
• a first data buffer for receiving data from an I/O device in units of a first byte length and sending data to the I/O device in units of said first byte length, and
• an address register for storing an address of said first data buffer;
• and
• a channel control unit, said channel control unit including:
• a plurality of holding means each being provided for each channel device, and each being coupled to said address register of said channel device for holding an address of a main storage unit at which address the data to be transferred to and transferred from the I/O device is stored, wherein said address register holds a copy of lower bits of said address held in said holding means, and
• a second data buffer, said second data buffer receiving data from one of the channel devices in units of a second data byte length and sending data to one of the channel devices in units of said second byte length, which data is accessed based on the address designated by said holding means, said second data buffer receiving data from the main storage unit in units of a third byte length and sending data, received from one of said channel devices, to the main storage unit in units of said third byte length;
• and wherein said second byte length is larger than said first byte length, and said third byte length is larger than said second byte length.

A data transfer apparatus comprising:

• a plurality of channel devices wherein each channel device receives data of a first bit width from a corresponding I/O device, each of the plurality of channel devices including:
• an address register, first buffer for storing, beginning at an address designated by said address holder means, the data of a first bit width from the I/O device, and,
• means for reading out data of a second bit width from the first buffer, wherein the data of the second bit width have a larger number of bits than the data of the first bit width;
• a channel control unit said channel control unit including:
• a plurality of first address holding means, each first address holding means corresponding to one of the channel devices and being coupled to said address register of said one channel device, for holding an address of a main storage unit at which data from the corresponding channel device is stored, wherein said address register holds a copy of the lower bits of said address held in said first address holding means, and
• a second data buffer, accessed based on the address designated by the first address holding means, for storing data received from the channel device;
• a first data bus having a large enough bit width to carry data of the first bit width in a parallel fashion as a data transmission between the first data buffer and the I/O device;
• and
• a second data bus having a large enough width to carry data of the second bit width in a parallel fashion as a data transmission between the first and second data buffers wherein the second data bus has larger bit capacity than that of the first data bus.