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US 4,788,509 AGranted
Phase shifter
AssigneeITT Gallium Arsenide Technology Center, a division of ITT Corporation
InventorsInder J. Bahl, Gary K. Lewis
Life of this patent
Estimating the term…
Abstract
A multifunction monolithic microwave integrated circuit composed of a pluity of dual gate FET amplifier sections connected between a pair of transmission lines which are adapted to receive one or two input signals. The circuit can be configured, by selective external connections and biasing voltage levels, to function in a number of different modes, such as an amplifier, a mixer, modulator, a variable amplifier, an attenuator, a temperature compensation chip, a frequency multiplier and a phase shifter.
Claims4
A multifunction circuit configured to function as a phase shifter comprising:
- a first monolithic microwave integrated circuit including
- a plurality of FET amplifier sections, each section having an output and a FET with a first and a second gate;
- output means coupled to the outputs of said amplifier sections for providing an output signal representative of the combined output of said amplifier sections;
- a first transmission line having a plurality of matching networks and first input means adapted for receiving a microwave input signal, said first gates connected to said first transmission line and separated one from another by a respective matching network of said first transmission line and first biasing means for applying a bias to said first gates;
- a second transmission line having a plurality of matching networks and second input means adapted for receiving a microwave input signal, said second gates connected to said second transmission line and separated one from another by a respective matching network of said second transmission line and second biasing means for applying a bias to said second gates, said first and second biasing means selecting drain source current and thereby an operating region of said FETs;
- a first biasing voltage source coupled to said first biasing means;
- a second biasing voltage source coupled to said second biasing means;
- a second multifunction monolithic microwave integrated circuit including
- a plurality of FET amplifier sections, each section having an output and a FET with a first and a second gate;
- output means coupled to the outputs of said amplifier sections for providing an output signal representative of the combined outputs of said amplifier section;
- a first transmission line having a plurality of matching networks and first input means adapted for receiving a microwave input signal, said first gates connected to said first transmission line and separated one from another by a respective matching network of said first transmission line and first biasing means for applying a bias to said first gates;
- a second transmission line having a plurality of matching networks and second input means adapted for receiving a microwave input signal, said second gates connected to said second transmission line and separated one from another by a respective matching network of said second transmission line and second biasing means for applying a bias to said second gates, said first and second biasing means selecting drain source current and thereby an operating region of said FETs;
- a first biasing voltage source coupled to said first biasing means;
- a second biasing voltage source coupled to said second biasing means;
- a coupler having a coupler input node for receiving a microwave input signal and two coupler output nodes, each coupler output node individually connected to one of said input means of each of said monolithic microwave integrated circuits, respectively;
- and
- combiner means having two combiner inputs each coupled to said output means of one of said multifunction monolithic microwave integrated circuits for combining the respective output signals and providing a phase shifted representation of said coupler input signal.
14 more elements
A phase shifter comprising:
- a first monolithic microwave integrated circuit including
- a plurality of FET amplifier sections, each section having an output and a FET with a first and a second gate;
- output means coupled to the outputs of said amplifier sections for providing an output signal representative of the combined outputs of said amplifier sections;
- a first transmission line having a plurality of matching networks and first input means adapted for receiving a microwave input signal, said first gates connected to said first transmission line and separated one from another by a respective matching network of said first transmission line and first biasing means for applying a bias to said first gates;
- a second transmission line having a plurality of matching networks and second input means adapted for receiving a microwave input signal, said second gates connected to said second transmission line and separated one from another by a respective matching network of said second transmission line and second biasing means for applying a bias to said second gates, said first and second biasing means selecting drain source current and thereby an operating region or said FETs;
- a first biasing voltage source coupled to said first biasing means;
- a second biasing voltage source coupled to said second biasing means;
- a second monolithic microwave integrated circuit including
- a plurality of FET amplifier sections, each section having an output and a FET with a first and a second gate;
- output means coupled to the outputs of said amplifier sections for providing an output signal representative of the combined outputs of said amplifier sections;
- a first transmission line having a plurality of matching networks and first input means adapted for receiving a microwave input signal, said first gates connected to said first transmission line and separated one from another by a respective matching network of said first transmission line and first biasing means for applying a bias to said first gates;
- a second transmission line having a plurality of matching networks and second input means adapted for receiving a microwave input signal, said second gates connected to said second transmission line and separated one from another by a respective matching network of said second transmission line and second biasing means for applying a bias to said second gates, said first and second biasing means selecting drain source current and thereby an operating region of said FETs;
- a first biasing voltage source coupled to said first biasing means;
- a second biasing voltage source coupled to said second biasing means;
- a coupler having a coupler input node for receiving a microwave input signal and two coupler output nodes, each coupler output node individually connected to one of said input means of each of said monolithic microwave integrated circuits, respectively;
- and
- combiner means having two combiner inputs each coupled to said output means of one of said monolithic microwave integrated circuits for combining the respective output signals and providing a phase shifted representation of said coupler input signal.
14 more elements
A phase shifter comprising:
- a first circuit including
- a plurality of FET amplifier sections, each section having an output and a FET with a first and a second gate;
- output means coupled to the outputs of said amplifier sections for providing an output signal representative of the combined outputs of said amplifier sections;
- a first transmission line having a plurality of matching networks and first input means adapted for receving a microwave input signal, said first gates connected to said first transmission line and separated one from another by a respective matching network of said first transmission line and first biasing means for applying a bias to said first gates;
- a second transmission line having a plurality of matching networks and second input means adapted for receiving a microwave input signal, said second gates connected to said second transmission line and separated one from another by a respective matching network of said second transmission line and second biasing means for applying a bias to said second gates, said first and second biasing means selecting drain source current and thereby an operating region of said FETs;
- a first biasing voltage source coupled to said first biasing means;
- a second biasing voltage source coupled to said second biasing means;
- a second circuit including
- a plurality of FET amplifier sections, each section having an output and a FET with a first and a second gate;
- output means coupled to the outputs of said amplifier sections for providing an output signal representative of the combined outputs of said amplifier sections;
- first transmission line having a plurality of matching networks and first input means adapted for receiving a microwave input signal, said first gates connected to said first transmission line and separated one from another by a respective matching network of said first transmission line and first biasing means for applying a bias to said first gates;
- a second transmission line having a plurality of matching networks and second input means adapted for receiving a microwave input signal, said second gates connected to said second transmission line and separated one from another by a respective matching network of said second transmission line and second biasing means for applying a bias to said second gates, said first and second biasing means selecting drain source current and thereby an operating region of said FETs;
- a first biasing voltage source coupled to said first biasing means;
- a second biasing voltage source coupled to said second biasing means;
- a coupler having a coupler input node for receiving a microwave input signal and two coupler output nodes, each coupler output node individually connected to one of said input means of each of said circuits, respectively;
- and
- combiner means having two combiner inputs each coupled to said output means of one of said circuits for combining the respective output signals and providing a phase shifted representation of said coupler input signal.
14 more elements
Dependencies are inferred from the claim text.