Speed control system for DC motor
AssigneeNEC Corporation
InventorsEiichi Ishii, Masuo Osuga
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Abstract
A speed control system for a DC motor is disclosed. This system includes a first transistor connected between a first terminal and a reference terminal, a second transistor connected between a second terminal and the reference terminal, an error amplifier having first input terminal connected via a reference voltage circuit to the first terminal, a second input terminal connected to a third terminal and an output terminal connected to the bases of the first and second transistors, a first resistor connected between a power terminal and the second terminal, a second resistor connected between the first and third terminals, and a third resistor connected between the second and third terminals, and the motor is connected between the first terminal and the power terminal.
Claims10
A motor speed control system comprising a power supply terminal, first, second and third terminals, a reference terminal, a motor connected between said power supply terminal and said first terminal, a first resistor connected between said power supply terminal and said second terminal, a second resistor connected between said first and third terminals, a third resistor connected between said second and third terminals, a first transistor having a collector-emitter path connected between said first and reference terminals, a second transistor having a collector-emitter path connected between said second and reference terminals, an error amplifier having first and second input terminals and an output terminal which is connected to bases of said first and second transistors, means coupled between said first terminal and said first input terminal of said error amplifier for generating a reference voltage thereacross, and means for connecting said third terminal to said second input terminal of said error amplifier.
A circuit combination comprising a first transistor having a collector-emitter path connected between a first terminal and a reference terminal, a second transistor having a collector-emitter path connected between a second terminal and said reference terminal, an error amplifier having first and second input terminals and an output terminal which is connected in common to bases of said first and second transistors, a bias current source connected between a power terminal and said first input terminal of said error amplifier and producing a bias current, a reference voltage circuit connected between said first terminal and said first input terminal of said error amplifier and generating a reference voltage in response to said bias current, a motor connected between said first terminal and said power terminal, a first resistor connected between said second terminal and said power terminal, second and third resistors connected in series between said first and second terminals, and means for level-shifting a potential at the node of said second and third resistors to supply the level-shifted potential to said second input terminal of said error amplifier.
An integrated circuit device for a motor speed control, comprising first, second, third, fourth and fifth terminals, first and second transistors each having a base, an emitter and a collector, first means for connecting the collector of said first transistor to said first terminal, second means for connecting the collector of said second transistor to said second terminal, third means for connecting the emitters of said first and second transistors to said fourth terminal, a differential amplifier having first and second input terminals and an output terminal, fourth means for connecting said output terminal of said differential amplifier to the bases of said first and second transistors, fifth means for connecting said first input terminal of said differential amplifier to said third terminal, a reference voltage circuit connected between said first terminal and said second input terminal of said differential amplifier, and a bias current source connected between said fifth terminal and said second input terminal of said differential amplifier.
Dependencies are inferred from the claim text.