Circuit arrangement of sense amplifier for rapid evaluation of logic state

A sense amplifier circuit for use in a semiconductor memory device including a memory cell array having a plurality of memory cells arranged in rows and columns, a row selector selecting a row of memory cells, a column selector selecting a column of memory cells and having an output node to which a high voltage level or a low voltage level appears depending upon a piece of information stored in one of said memory cells specified by both of the row and column selectors, a reference voltage producing circuit and a comparator having two input nodes one of which is connected to the reference voltage producing circuit, comprising

• (a) a signal input node connected to the output node of said column selector;
• (b) a signal output node connected to the other of the input nodes of said comparator;
• (c) a series combination of n-channel shallow depletion-type field effect transistors coupled between a source of positive voltage and said signal output node, said n-channel shallow depletion-type field effect transistors having respective gate electrodes connected to said source of positive voltage so as to provide a relatively large resistance;
• (d) a first n-channel enhancement-type field effect transistor with a relatively small channel resistance coupled between said signal output node and said signal input node and having a gate electrode;
• (e) a second n-channel enhancement-type field effect transistor with a relatively small channel resistance coupled between said positive voltage source and said signal output node and having a gate electrode, said second n-channel enhancement-type field effect transistor having a threshold voltage approximately equal to that of said first n-channel enhancement-type field effect;
• and
• (f) a NOR gate having an output node connected to both of the gate electrodes of said first and second n-channel enhancement-type field effect transistors and two input nodes one of which is connected to said signal input node and the other of which is capable of being supplied with an activating signal.

A sense amplifier circuit comprising

• (a) a signal input node;
• (b) a signal output node;
• (c) load means with a relatively large resistance coupled between a source of voltage and said signal output node;
• (d) a first field effect transistor with a relatively small channel resistance coupled between said signal input node and said signal output node and having a gate electrode;
• (e) a logic gate having at least one input node connected to said signal input node and an output node connected to the gate electrode of the first field effect transistor;
• and
• (f) a second field effect transistor with a relatively small channel resistance with respect to said first field effect transistor, said second field effect transistor being coupled between said source of voltage and said signal output node and having a gate electrode connected to the output node of said logic gate, in which said load means comprise a series combination of a first n-channel depletion-type field effect transistor, an intermediate node and a second n-channel depletion-type field effect transistor coupled between said source of voltage producing a positive voltage level and said signal output node for providing a current path therebetween, said first and second n-channel depletion-type field effect transistors having respective gate electrodes connected to said intermediate node and said signal output node, respectively, wherein said first and second field effect transistors are of an n-channel enhancement-type and said logic gate performs a NOT operation.

A sense amplifier circuit comprising

• (a) a signal input node;
• (b) a signal output node;
• (c) load means with a relatively large resistance coupled between a source of voltage and said signal output node;
• (d) a first field effect transistor with a relatively small channel resistance coupled between said signal input node and said signal output node and having a gate electrode;
• (e) a logic gate having at least one input node connected to said signal input node and an output node connected to the gate electrode of the first field effect transistor;
• and
• (f) a second field effect transistor with a relatively small channel resistance with respect to said first field effect transistor, said second field effect transistor being coupled between said source of voltage and said signal output node and having a gate electrode connected to the output node of said logic gate, in which said load means comprise a series combination of a first n-channel shallow depletion-type field effect transistor, an intermediate node and a second n-channel shallow depletion-type field effect transistor coupled between said source of voltage producing a positive voltage level and said signal output node for providing a current path therebetween, said first and second n-channel shallow depletion-type field effect transistors having respective gate electrodes connected to said source of voltage, wherein said first and second field effect transistors are of an n-channel enhancement-type, and said logic gate has two input nodes, one of said two input nodes being connected to said signal input node, and performs a NOR operation in the presence of an activating signal applied to the other of two input nodes for activation of the logic gate.