US 4,788,457 AGranted

CMOS row decoder circuit for use in row and column addressing

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsKoichiro Mashiko, Kazutami Arimoto, Kiyohiro Furutani, Noriaki Matsumoto, Yoshio Matsuda

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Abstract

A CMOS row decoder circuit in which a row decoder for selecting a single word line from a memory cell array and a column decoder for selecting a single bit line can use in common an internal address signal transmission line. The row decoder circuit comprises a series of MOSFETs of a first conductivity type which is turned on or off in response to address signals selected from external address signals, a second MOSFET of a second conductivity type provided between a power supply potential and the series of MOSFETs and having a gate receiving a first timing signal for providing decoding timing of the address signals, a third MOSFET of the first conductivity type provided between the series of MOSFETs and the second MOSFET and having a gate receiving a first operation timing signal, a fourth MOSFET which is turned on or off in response to a second operation timing signal for transmitting the potential of a node of the second MOSFET and the third MOSFET, and a fifth MOSFET having a gate receiving an output of the fourth MOSFET for transmitting a word line driving signal to a corresponding word line.

Claims4

Dependent claims

A row decoder circuit having a CMOS structure receiving a plurality of address signals included in external address signals for decoding the same, transmitting a word line driving signal produced in accordance with said external address signals to a word line and selecting the word line based on the decoded result, comprising:

a plurality of first MOS transistors of a first conductivity type connected in series with each other and each having a gate receiving one of said plurality of address signals,
a second MOS transistor of a second conductivity type connected between said plurality of first MOS transistors connected in series with each other and a power supply potential and having a gate receiving a first operation timing signal for providing decoding timing of said plurality of address signals,
a third MOS transistor of the first conductivity type connected between said plurality of first MOS transistors connected in series with each other and said second MOS transistor and having a gate receiving said first operation timing signal,
a fourth MOS transistor having a gate receiving a second operation timing signal for transmitting a signal corresponding to an output of a node between said second MOS transistor and said third MOS transistor, and
a fifth MOS transistor of the first conductivity type having a gate receiving a signal transmitted through said fourth MOS transistor for transmitting the applied word line driving signal to the word line connected thereto.

2 more elements

Dependencies are inferred from the claim text.