Power-on reset circuit
AssigneeOki Electric Industry Co., Ltd.
InventorsKouji Tanagawa, Tomoaki Yoshida
Life of this patent
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Abstract
A reset circuit for a logic circuit comprises a MOS transistor having a gate coupled to a power supply, a source receiving a reset input and a drain whose potential is high when the reset input is high and the power supply voltage drops below a predetermined threshold, a flip-flop connected to be set when the drain of the MOS transistor is high and reset when the reset input is low, and a circuit producing a reset output when the flip-flop is in the set state, the reset output being applied to the logic circuit.
Claims16
A reset circuit for a logic circuit, said logic circuit having a reference ground potential, comprising:
- a MOS transistor having a gate coupled to a power supply, a source receiving an external reset input signal, and a drain, said drain having a high potential when the external reset input signal is high and the voltage of said power supply drops below a predetermined threshold;
- a flip-flop having a set input connected to the drain of said MOS transistor, said flip-flop being set to produce an internal reset signal when the drain of said MOS transistor is high and being reset when the external reset input signal is low;
- means for producing a reset output from said flip-flop when said flip-flop is in the set state;
- and
- means for applying said reset output to said logic circuit.
Dependencies are inferred from the claim text.