Preamble search and synchronizer circuit

A preamble search and synchronizer circuit for detecting a preamble pattern within data input signals and for synchronizing it with a clock signal associated with a starLAN coded data transceiver, said preamble search and synchronizer circuit comprising:

• input means for receiving data input signals and a clock signal and for generating the complement of the data input signals and the complement of the clock signal;
• synchronizer start means responsive to the complement of the data input signals and the uncomplemented clock signal for generating a start signal which is synchronized with the uncomplemented clock signal;
• counter means responsive to the start signal and the complement of the clock signal for generating a first gated clock signal and a second gated clock signal;
• pattern detector means responsive to the start signal, the data input signals, the first gated clock signal and the second gated clock signal for sampling the data input signals and for generating a synchronized output signal upon detection of the preamble pattern;
• and
• said pattern detector means including shift register means connected to receive the first gated clock signal for shifting the sampled input signals and decoder means connected to the outputs of said shift register means and the second gated clock signal for detecting the preamble pattern.

A preamble search and synchronizer circuit comprising:

• input means for receiving data input signals and a clock signal and for generating the complement of the data input signals and the complement of the clock signal;
• synchronizer start means responsive to the uncomplemented clock signal and complement of the data input signals for generating a start signal which is synchronized with the uncomplemented clock signal;
• counter means responsive to the start signal and the complement of the clock signal for generating a gated clock signal;
• and
• pattern detector means responsive to the start signal, the data input signals and the gated clock signal for sampling the data input signals and for generating a synchronized output signal upon detection of a preamble pattern contained within the data input signals.