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US 4,787,068 AGranted
MOS-type memory circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorYuji Kihara
Life of this patent
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Abstract
A MOS-type memory circuit comprising a terminal end potential feeder circuit which applies a voltage of certain level between a supply voltage and a ground potential to terminal ends of word lines when memory addresses change-over.
Claims11
A MOS-type memory circuit comprising:
- a plurality of memory cells arranged in a matrix,
- word lines, each of which is connected to a row of said memory cells, said word lines having base ends receiving signals to access memory cells at different addresses, and said word lines having terminal end, and
- a terminal end potential feeder circuit which applies a predetermined voltage having a potential level between a supply voltage and a ground potential to said terminal ends of said word lines during an address transition to speed up access by reducing voltage swing at said terminal ends of said word lines to reach steady state values determined by the signals applied to said base ends of said word lines.
A MOS-type memory circuit comprising:
- a plurality of memory cells arranged in a matrix shape,
- bit lines, each of which is connected to the memory cells, arranged in a corresponding column,
- word lines, each of which is connected to the memory cells, arranged in a corresponding row and has an initial end fed with a potential conforming to an address input, said word lines having terminal ends,
- an address transition detection (ATD) pulse generator which generates a pulse upon sensing that the address input has changed,
- a potential generator connected to said ATD pulse generator and delivering a predetermined voltage to an output end thereof responsive to the pulse from said ATD pulse generator, which predetermined voltage is at a potential level between a supply voltage and a ground potential, and
- switching means connected to said ATD pulse generator and between the terminal ends of said word lines and the output end of said potential generator and operated so as to conduct upon receiving the pulse generated by said ATD pulse generator, connect the predetermined voltage to the terminal ends of said word lines, and speed up access to said memory cell by reducing voltage swing at the terminal ends of said word lines.
3 more elements
Dependencies are inferred from the claim text.