Semiconductor dynamic memory device having improved refreshing

A semiconductor dynamic memory device having read/write and refreshing operations controlled by RAS and CAS signals applied from external circuits, comprising:

• a memory cell array for storing data;
• a word decoder for decoding an address signal applied thereto and selecting word lines of said memory array;
• a refresh address counter for generating a refresh address signal;
• a CAS before RAS detector means, for detecting the levels of the CAS signal and RAS signal applied to said memory device, and for providing an external address driving signal ADE when it discriminates that the CAS signal is high level when the RAS signal becomes low level, and for providing a refresh address driving signal ADI when it discriminates that the CAS signal is low level when the RAS signal becomes low level;
• an external address buffer means, coupled to said detector means, for latching an external address sent to the dynamic memory device from the external circuit, and sending the latched address to said word decoder when said address buffer means receives the ADE signal;
• and
• a refresh address buffer means, coupled to said detector means in parallel with said external address buffer means, for latching the refresh address generated by said refresh address counter and sending the latched address to said word decoder when said refresh address buffer means receives the ADI signal,
• wherein said external address and said refresh addresses are simultaneously processed in parallel in said external address buffer means and said refresh address buffer means respectively, such that one of said external address or said refresh address can be immediately applied to said word decoder in response to one of said ADE or ADI signals respectively.