Data processing apparatus providing cyclic addressing of a data store in selectively opposite directions

A data processing apparatus comprising:

• a random access memory for storing data in a plurality of addresses therein;
• an address register for storing and accessing any address in said memory;
• an incrementation circuit connected to said address register for selectively incrementing or decrementing the address stored therein;
• a first auxiliary register for storing a minimum address value;
• a second auxiliary register for storing a maximum address value;
• address comparison means having a first input connected to said address register, a second input selectively connectable to either of said first and second auxiliary registers, and an output at which an equality signal is produced when an address signal at the first input matches an address signal at the second input;
• and
• address cycling means for controlling the cyclic accessing of successive addresses in said memory in opposite directions between said minimum and maximum address values, such address cycling means having first and second operating states such that:
• (i) in said first operating state said address cycling means actuates said incrementation circuit to increment the address in said address register;
• connects the second auxiliary register to said second input of said address comparison means;
• and, in response to an equality signal produced at the output of said address comparison means, connects the first auxiliary register to said address register to load said minimum address value therein;
• and
• (ii) in said second operating state said address cycling means actuates said incrementation circuit to decrement the address in said address register;
• connects the first auxiliary register to said second input of said address comparison means;
• and, in response to an equality signal produced at the output of said address comparison means, connects the second auxiliary register to said address register to load said maximum address value therein;
• whereby the data in said random access memory at addresses therein between said minimum and maximum address values may be cyclically accessed in selectively opposite directions.