Circuit for calculating the discrete Fourier transform
AssigneeThomson-CSF
InventorsGerard Bergeon, Claude Legendre, Marc Muller, Philippe Cros, Jean-Louis Lemaire
Life of this patent
Estimating the term…
Abstract
A circuit for calculating the discrete Fourier transform which includes a multiplier, two adders for effecting the calculation of the discrete Fourier transform while describing a butterfly data path, and address processors which supply the multiplier and adders with continuous data under the control of a synchronization clock. To accelerate the calculations, the processor has a memory for reducing the data access time. This memory is divided into two parts, each of which alternately plays the role of calculation memory and input/output memory for the transfer of data with a memory external to the processor.
Claims17
A circuit for calculating the discrete Fourier transform, comprising
- means (190) for providing time discrimination including
- a multiplier (41), having a pair of inputs (53, 107) and an output, and
- a first adder (42) having a pair of inputs, a first one (59) of which is connected to said multiplier output, and a second one (68) of which is connected to a data stream (55) not passing through said multiplier (41), and
- a second adder (43) having a pair of inputs, a first one (56) of which is connected directly to said multiplier output, and a second one (57) of which is connected to a buffer memory (63), said buffer memory (63) being coupled to said multiplier output, said connections of said first and second adders thereby defining a butterfly data stream configuration,
- means (500, 124-131) for breaking up calculation of the transform over N points into a succession of independent Fourier transform calculations over groups of N.sub.i terms, where N is greater than N.sub.i, and including address processor means (125,128) for supplying continuous streams of data (51, 100) to said time discrimination means (190).
A circuit for calculating the discrete Fourier transform, comprising
- means (190) for providing time discrimination including
- a multiplier (41), having a pair of inputs (53, 107) and an output, and
- a first adder (42) having a pair of inputs, a first one (59) of which is connected to said multipler output, and a second one (68) of which is connected to a data stream (55) not passing through said multiplier (41), and
- a second adder (43) having a pair of inputs, a first one (56) of which is connected directly to said multiplier output, and a second one (57) of which is connected to a buffer memory (63), said buffer memory (63) being coupled to said multiplier output, said connections of said first and second adders thereby defining a butterfly data stream configuration,
- means (500, 124-131) for breaking up calculation of the transform over N points into a succession of independent Fourier transform calculations over groups of N.sub.i terms, where N is greater than N.sub.i, and including address processor means (125,128) for supplying continuous streams of data (51, 100) to said time discrimination means (190), and
- input/output processor means (129), within said breaking up means (124-131), for managing data exchange (100,155) between
- an internal memory (130,131) and
- an external memory (646,647), and wherein said internal memory is divided into two blocks (130,131) each acting alternately as calculation memory and as input-output memory.
Dependencies are inferred from the claim text.