Electrically erasable fused programmable logic array

A programmable logic array comprising:

• a plurality of logic array input means for receiving a plurality of input logic signals;
• a plurality of logic gates, each gate having a plurality of inputs;
• a plurality of fuse means, each fuse means having an output independent of, and not directly connected to, the output of any other fuse means and each input of each logic gate being selectively connected to a different fuse means output than any other logic gate input whereby the output of each fuse means is connected to only one input of said logic gates for connecting the output of each fuse means to only one input of a logic gate and each logic gate input to only one fuse means output, each fuse means having programmable logic states, for alterably coupling selected ones of said input means to selected ones of said logic gate inputs by performing the NAND logic operation on the input logic signals received by said fuse means from said selected ones of said input means and the programmed logic state of said fuse means and providing the logic output of said NAND operation to said selected ones of said logic gates;
• and
• programming means for programming selected ones of said fuse means.

A CMOS integrated circuit programmable logic array comprising:

• a plurality of inputs for receiving a plurality of input logic signals;
• a plurality of logic gates each logic gate having a plurality of inputs;
• a plurality of electrically erasable fuse means each having an output independent of, and not directly connected to, the output of any other electrically erasable fuse means, and the inputs of each logic gate being connected to the outputs of a selected number of electrically erasable fuse means, each logic gate being connected to a different number of electrically erasable fuse means than any other logic gate, for selectively logically coupling selected ones of said inputs to selected ones of said logic gates and for connecting the output of each fuse means to only one input of a logic gate and each logic gate input to only one fuse means output;
• a plurality of program signal control means coupled to selected ones of said logic gates and selected ones of said fuse means, for selectively supplying a programming signal to said selected ones of said fuse means;
• and
• a plurality of erase signal control means coupled to selected ones of said fuse means and selected ones of said inputs, for selectively supplying erase signals to said selected ones of said fuse means;
• wherein said fuse means is selectively programmed into one of two programming states by selective application of predetermined level signals to said inputs, said program signal control means, and said erase signal control means.

A programmable logic array comprising:

• a plurality of input means for receiving a plurality of input signals;
• a plurality of logic gates each having a plurality of inputs;
• a plurality of programmable transistor fuse means, each programmable transistor fuse means having an output independent of, and not connected to, the output of any other fuse means, and each one of said plurality of inputs of each logic gate being connected to a different, selected, output of a programmable transistor fuse means than any other logic gate input for connecting the output of each fuse means to only one input of a logic gate and each logic gate input to only one fuse means output, each programmable transistor fuse means having two programming logic states, for providing a relatively constant load conductive current path when in a first one of said two programming states during normal logic operations and a substantially nonconductive path when in the second of said two programming states during normal logic operations;
• and
• each means including a programmable transistor and one or more transistor means coupled to said programmable transistor means and said input means and said output means, for providing the NAND logic operation in conjunction with said programmable transistor means on the logic level of said input signal and the logic state of the programmable transistor means and outputting the NAND logical output thereof;
• a plurality of program signal control means coupled to selected ones of said logic gates and selected ones of said fuse means, for selectively supplying a programming signal to said selected ones of said programmable transistor means;
• and
• a plurality of erase signal control means coupled to selected ones of said programmable transistor fuse means and selected ones of said input means, for selectively supplying erase signals to said selected ones of said programmable transistor fuse means;
• wherein each one of said programmable transistor fuse means is selectively programmed into one of said two programming states by selective application of predetermined level signals to said input means, said program signal control means, and said erase signal control means.

A programmable logic array comprising:

• a plurality of inputs for receiving a plurality of input logic signals;
• a plurality of logic gates each having a plurality of inputs;
• a plurality of electrically erasable fuse means each having an output independent of, and not directly connected to, the output of any other electrically erasable fuse means, and the inputs of each logic gate being connected to the outputs of a selected number of electrically erasable fuse means, each logic gate being connected to a different number of electrically erasable fuse means than any other logic gate, for selectively logically coupling selected ones of said inputs to selected ones of said logic gates and for connecting the output of each fuse means to only one input of a logic gate and each logic gate input to only one fuse means output;
• a plurality of program signal control means equal in number to said plurality of logic gates and coupled to selected ones of said electrically erasable fuse means, for selectively supplying a programming signal to said selected ones of said fuse means;
• and
• a plurality of erase signal control means equal in number to said plurality of inputs and coupled to selected ones of said electrically erasable fuse means, for selectively supplying erase signals to said selected ones of said fuse means;
• wherein said electrically erasable fuse means is selectively programmed into one of two programming states by selective application of predetermined level signals to said inputs, said program signal control means, and said erase signal control means.

In a programmable logic gate array of reprogrammable fuses arranged in rows and columns, each reprogrammable fuse comprising:

• input means for receiving a logic input signal;
• output means;
• a first programmable transistor and a second transistor of one conductivity type, a third transistor of complementary conductivity type;
• each one of said transistors having first and second electrodes defining the ends of a conduction path and a control electrode;
• said programmable transistor having two programming logic states, for providing a relatively constant load conductive current path when in a first one of said two programming states during normal logic operations and a nonconductive path when in the second of said two programming states during normal logic operations;
• means serially connecting the conduction paths of said first and second transistors between said output means and a first point of operating potential;
• means connecting the conduction path of said third transistor between said output means and a second point of operating potential;
• and
• means for coupling the control electrodes of said second and third transistors to said input means for providing the NAND logic operation in conjunction with said programmable transistor means on the logic level of said input signal an the logic state of the programmable transistor means and outputting the NAND logical output thereof.

In a programmable logic gate array of electrically erasable fuses arranged in rows and columns, each erasable fuse comprising:

• input means for receiving an input signal;
• an output;
• first and second points of operating potential;
• a programmable transistor having two programming logic states;
• said programming transistor having first and second electrodes defining the ends of a conduction path and a control electrode;
• a first transistor of one conductivity type and a second transistor of second conductivity type, each transistor having first and second electrodes defining the ends of a conduction path and a control electrode;
• means serially connecting the conduction paths of said first transistor and said programmable transistor between said output and said first point of operating potential and means connecting said second transistor between said output and said second point of operating potential and means coupling said input means to the control electrodes of said first and second transistors for providing at said output the logically inverted signal to the input signal provided at said input when said programmable transistor is in a first programming state and providing a fixed logic signal at said output when said programmable transistor is in the second of said two programming states;
• and
• means coupled to the control electrode and one end of the conduction path of said programmable transistor for programming said programmable transistor.

A programmable logic array comprising:

• a plurality of logic input means for receiving a plurality of input logic signals;
• a plurality of electrically alterable programmable fuse means each having an input and an output and each being programmable into either a first state in which said electrically alterable programmable fuse means operates as a logic inverter or into a second state in which said electrically alterable programmable fuse means provides at its output a preselected fixed logic signal said plurality of electrically alterable programmable fuse means being arranged in "N" rows, each having "M" columns;
• "N" logic gates, one logic gate per row of electrically alterable programmable fuse means each gate having "M" inputs;
• means for coupling the outputs of the "M" electrically alterable programmable fuse means of each row to a different one of the "M" inputs of its corresponding logic gate for connecting the output each fuse means to only one input of a logic gate and each logic gate input to only one fuse means output;
• and
• programming means for selectively programming said programmable fuse means;
• where M is an integer greater than two.