US 4,787,041 AGranted

Data control system for digital automatic flight control system channel with plural dissimilar data processing

AssigneeHoneywell Inc.

InventorLarry J. Yount

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Abstract

A direct memory access (DMA) system with a single bus architecture for controlling data transfers and storage between plural digital processors and plural Input/Output devices. Limiters are included for disabling access to the bus of a processor whose access time exceeds a predetermined time interval. A time governor is included to suppress processor access to the bus when total processor access time in a data communication cycle has exceeded a predetermined time interval. The input and output devices are coupled to the bus through interface isolation circuits that prevent faults in the input and output devices from propagating to the system to cause total system failure. An input or output device fault can only result in erroneous data being provided to a location of the DMA memory reserved for the faulted device. The DMA memory is protected by a Write-Protect Decoding Circuit that prevents processor writing into prohibited areas of the memory.

Claims18

Dependent claims

A channel for an automatic flight control system comprising:

a set of input devices,
a set of output devices,
a first digital processor,
a second digital processor,
a data control system intercoupling said set of input devices, said set of output devices, said first digital processor and said second digital processor for transferring data signals, address signals and control signals therebetween, said first digital processor having access of said data control system for a first predetermined time interval and said second digital processor having access to said data control system for a second predetermined time interval,
first limiter means associated with said first digital processor for disabling access of said first digital processor to said data control system whenever said first digital processor maintains access thereto for a time interval greater than said first predetermined time interval,
second limiter means associated with said second digital processor for disabling access of said second digital processor to said data control system whenever said second digital process maintains access thereto for a time interval greater than said second predetermined time interval.

4 more elements

Dependencies are inferred from the claim text.