Priority arbitration circuit for processor access

A personal computer with a high speed microprocessor compatible with applications software written for slower speed microprocessors comprising:

• (a) a high speed microprocessor with a real and protected mode electrically coupled to a high speed data bus;
• (b) non-volatile memory electrically coupled to a slow speed data bus;
• (c) bus controller electrically coupling the high speed data bus to the slow speed data bus;
• (d) dynamic memory electrically coupled to the high speed data bus;
• (e) at least one input/output device coupled to said slow speed data bus;
• (f) first microprocessor instruction halting means responsive to dynamic memory refresh cycle, said cycle repeatably occurring at timed intervals to generate a first microprocessor hold request;
• (g) second microprocessor instruction halting means responsive to a direct memory access (DMA) request to generate a second microprocessor hold request;
• (h) first arbitration means to arbitrate said first microprocessor hold request and said second microprocessor hold request to generate an arbitrated microprocessor hold request;
• (i) switching means for switching the microprocessor from the real to protected mode and from protected to real mode, said switching means generates a microprocessor reset cycle when the microprocesor returns from the protected mode to the real mode;
• and
• (j) detection means to detect the occurrence of an arbitrated microprocessor hold request during a microprocessor reset cycle to retain, for execution at a later time, the arbitrated microprocessor hold request generated during the execution of a microprocessor reset cycle.