Data processing apparatus with fixed address space

Data processing apparatus having a central processor connected to a plurality of ports to any or all of which may be attached a selection from a group of compatible devices, each incorporating means signifying its individual identity in terms distinguishing it from each of the others of said devices, some of the devices of the group including memory and a status register, requests for service from attached devices being ORed to the central processor, the central processor being arranged on power up and system reset to initialize and determine the function and location of the currently attached devices, the central processor including a memory accessing facility for accessing memory in terms of a fixed size address space and a register accessing facility for accessing individual registers in attached devices using register addresses which are independent of the memory address space, characterized in that

• (a) the initializing facility includes means for generating a (first) list associating the individual identity of each attached device including memory with the register address of the status register of that device;
• (b) the central processor is arranged to respond to a request for service by accessing the list and by indexing through the list, examining the status of each listed device in turn to determine if the currently examined device requested service and, if so, broadcasting the identity of that device followed by one or more memory addresses;
• and
• (c) each device having memory also including means for comparing each brodcast identity with the identity of the device and, on detecting equality, to latch the associated memory enabled to the exclusion of all of the others of said devices until the first detected inequality, and in that
• (d) the enabled device appears as a single entity to the central processor and occupies a single window in the address space which is common to all of said devices but used by them only one at a time.

A system comprising

• a processor,
• addressing means defining a finite memory address space, and
• a plurality of modules connectable into one common segment of said address space for access by said processor,
• each of said modules having address decoding means responsive to address in said common segment of said address space, at least one of said addresses being decodable by said decoding means of more then one of said modules,
• each of said modules having an identification indicium which is different from that of any of the other of said plurality of modules said decoding means of which is responsive to a same address,
• each of said modules having an identifier register writable by said processor for receiving identifier data broadcast to all of said plurality of modules by said processor, and
• each of said modules having comparison means sensitive to the contents of its said identifier register and operative upon and during a predetermined relationship of the contents of said register to the indicium of the module to enable that module to respond to a predetermined set of addresses comprising said one common segment so long as that module is enabled and to the exclusion of all other modules of said plurality of modules having a different identification indicium.