Level converting bus extender with subsystem selection signal decoding enabling connection to microprocessor
AssigneeGTE Communication Systems Corporation
InventorSalim M. Khan
Life of this patent
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Abstract
The bus extender circuit is a least replaceable unit which interfaces between intermodule subsystems and the microprocessor controller of the system. The bus extender circuits are structured so that the subsystem modules may be placed in different power zones. As a result, one subsystem may be powered down without affecting the other subsystems connected to the microprocessor's bus. In addition, the bus extender circuit converts from Fairchild Advanced Schottky TTL logic to high-speed CMOS logic and vice versa and allows bus interface gate arrays located in each subsystem to interface between the subsystem logic and the microprocessor. This bus extender circuit design eliminates the need for strapping options or DIP switches for address decoding.
Claims17
In a microprocessor system, a bus extender arrangement is connected between a microprocesor controller and a plurality of subsystems, said bus extender arrangement comprising:
- said microprocessor controller including microprocessor means;
- first gate array means connected to said microprocessor means for converting a plurality of signals of said microprocessor means from a first logic level to a second logic level;
- bus extender means including a plurality of bus extender circuit means, each bus extender circuit means including first level converting means connected between said first gate array means and said corresponding subsystem for converting said plurality of signals from said first to said second logic level, and second level converting means connected between said corresponding subsystem and said first gate array means for converting said plurality of signals from said second logic level to said first logic level;
- said plurality of subsystems each including second gate array means, and each subsystem connected via said corresponding bus extender circuit means to said microprocessor means, one at a time, for transferring data between said microprocessor means and one of said subsystems;
- selection signal means connected between said first gate array means and said bus extender means for addressing one of said plurality of subsystems;
- and
- each of said bus extender circuit means further including decoding means connected to said first gate array means, said corresponding subsystem and to said second level converting means, said decoding means operated in response to said operation of said selection signal means to enable said corresponding subsystem to connect to said microprocessor means.
Dependencies are inferred from the claim text.