Paging receiver

#This invention relates to a paging receiver and more particularly a paging receiver having an individual paging number and at least one common paging number.

#In advanced modern information communities importance of information has been increased drastically.

#As the amounts of information increase, many types of information receivers for reception of valuable information have been developed, including a receiver capable of receiving only paging numbers or signals, a receiver capable of also receiving a series of messages constituted by digits and letters, a receiver having multiaddresses, to improve receiving performance.

#In the accompanying drawings:

#FIGS. 1a to 1c are diagrams showing one example of the received signals utilized in this invention;

#FIG. 2 is a block diagram showing one embodiment of the display paging receiver in accordance with this invention;

#To facilitate understanding of the principle of this invention, one example of the received signals will first be described with reference to FIGS. 1a, 1b and 1c.

#In FIG. 1a, F designates a frame synchronizing signal, A an address signal, M a message signal and E an end signal. If necessary, a plurality of message signals M are used depending upon the length of a message.

#FIG. 1b shows a signal format wherein a signal comprising BCH (Bose-Chaudhuri-Hocquenghem) ending at 31st bit added with one parity bit at 32nd bit is used as the address signal or the message signal. This signal is made up of a 21-bit information area IA, 10-bit check area and 1-bit even parity bit EP, thus constituting one word with 32 bits. The information area utilizes its most significant bit (MSB) as an identification bit, and when its logic level is "0" this signal is processed as an address information signal, whereas when its logic level is "1" this signal is processed as a message information signal. Remaining 20 bits are used as the address information or message information.