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US 4,786,829 AGranted
Latched fedback memory finite-state-engine
OwnerJohn H. Letcherinventor
Life of this patent
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Abstract
Disclosed herein is a simple latched-fedback-memory finite-state-engine that produces an inherently stable output upon the receipt of a clock signal, that is synchronously or asynchronously generated. The finite-state-engine comprises at least three latches and a function module, wherein the output of one latch is used as an input for the function module and a previous output of the function module is re-entered as an input into the function module.
Claims9
A finite-state-engine comprising:
- a first latch means having as an input a data set X for producing an output X.sub.1 upon the receipt of a clock signal;
- function module means for storing at least one finite-state equation and having as an input X.sub.1 and Y.sub.1, and as an output Y.sub.1 ' and Y.sub.2 ';
- a second latch means having as an input Y.sub.1 ' for producing an output Y.sub.1 upon the receipt of the clock signal;
- and
- a third latch means having as an input Y.sub.2 ' for producing an output Y.sub.2 upon the receipt of a following clock signal.
2 more elements
Dependencies are inferred from the claim text.