CMOS Schmitt trigger circuit using ratioed currents to establish switching thresholds

A Schmitt trigger circuit comprising:

• a first MOS field effect transistor having its source connected to ground, an input signal applied to its gate and having a switching threshold controlled by the drain current thereof, wherein the first transistor functions as an inverter;
• a CMOS inverter having its input connected to the drain of the first transistor, wherein the output of the inverter is the output of the Schmitt trigger circuit;
• and
• switchable drain current supply means controlled by the output of the inverter for providing a drain current of a first or second value to the drain of the first transistor to control the switching threshold thereof, wherein when the output of the inverter is at a first level to drain current will have the first value and when the output of the inverter is at a second level the drain current will have the second value, thereby providing hysterisis to the circuit,
• the drain current supply means comprising:
• a second MOS transistor having its source connected to a power supply and its drain connected to the drain of said first transistor for supplying a first component of the drain current to the first transistor;
• a third MOS transistor having its source connected to a power supply for supplying a second component of the drain current to the first transitor;
• a fourth MOS transistor driven by the output of the CMOS inverter and connected between the drain of the third transistor and the drain of the first transistor, wherein the second transistor supplies the first component of drain current to establish the first value and wherein the third transistor supplies the second component of drain current when the fourth transistor is conductive, wherein the first and second components add to establish the second value of drain current;
• and
• control means for providing a fixed gate drive voltage to the gates of both the second and third transistors to provide a predetermined relationship between the first and second components of the drain current;
• wherein the control means includes a fifth MOS transistor having a predetermined drain current, wherein said fifth transistor is connected to both the second and third transistors in a current mirror configuration, wherein the relative sizes of the second, third and fifth transistors are controlled to provide said predetermined relationship between the first and second components of the drain current.

A Schmitt trigger circuit comprising:

• a first MOS field effect transistor of first conductivity type having its source connected to ground and an input signal applied to its gate;
• a complementary MOS inverter including a second MOS field effect transistor of first conductivity type having its source connected to ground and a third MOS field effect transistor of second conductivity type having its drain connected to the drain of the second transistor and its source coupled to a power supply, wherein the drain of the first transistor is connected to the gates of the second and third transistors and wherein the interconnected drains of the second and third transistors form the output of the inverter which is also the output of the Schmitt trigger circuit;
• a fourth MOS field effect transistor of second conductivity type having its gate connected to the output of the inverter and its drain connected to the drain of the first transistor;
• a fifth MOS field effect transistor of second conductivity type having its drain connected to the source of the fourth transistor and its source coupled to the power supply;
• a sixth MOS field effect transistor of second conductivity type having its drain connected to the drain of the first transistor and its source coupled to be supplied by the power supply;
• and
• bias means for controlling the value of drain currents of the fifth and sixth transistors, the bias means including a seventh MOS field effect transistor having its source coupled to the power supply and its drain connected to its gate and control means for controlling the drain current thereof, wherein the seventh transistor is connected to the fifth and sixth transistors in a current mirror configuration;
• wherein when the output of the inverter is at a first level, the switching threshold of the first transistor will be determined by the drain current of the sixth transistor alone and wherein when the output of the inverter is at a second level, the fourth transistor will be rendered conductive and the switching threshold of the first transistor will be determined by the drain currents of both the fifth and sixth transistors.

A Schmitt trigger circuit comprising:

• a first MOS field effect transistor of first conductivity type having its source connected to ground and an input signal applied to its gate;
• a complementary MOS inverter including a second MOS field effect transistor of first conductivity type having its source connected to ground and a third MOS field effect transistor of second conductivity type having its drain connected to the drain of the second transistor and its source coupled to a power supply, wherein the drain of the first transistor is connected to the gates of the second and third transistors and wherein the interconnected drains of the second and third transistors form the output of the inverter which is also the output of the Schmitt trigger circuit;
• a fourth MOS field effect transistor of second conductivity type having its gate connected to the output of the inverter and its drain connected to the drain of the first transistor;
• a fifth MOS field effect transistor of second conductivity type having its drain connected to the source of the fourth transistor and its source coupled to the power supply;
• a sixth MOS field effect transistor of second conductivity type having its drain connected to the drain of the first transistor and its source coupled to be suppled by the power supply;
• and
• bias means for controlling the value of drain currents of the fifth and sixth transistors, the bias means including a seventh MOS field effect transistor having its source coupled to the power supply and its drain connected to its gate and control means for controlling the drain current thereof, wherein the seventh transistor is connected to the fifth and sixth transistors in a current mirror configuration;
• wherein when the output of the inverter is at a first level, the switching threshold of the first transistor will be determined by the drain current of the sixth transistor along and wherein when the output of the inverter is at a second level, the fourth transistor will be rendered conductive and the switching threshold of the first transistor will be determined by the drain current of both the fifth and sixth transistors;
• wherein the control means includes an eigth MOS field effect transistor of first conductivity type having its drain connected to the drain of the seventh transistor, and its source connected to ground;
• and
• a voltage divider connected between power supply, ground and the gate of said eighth transistor for providing a predetermined voltage to the gate of the eighth transistor.