Method of making a monolithic integrated circuit comprising at least one bipolar planar transistor

An improvement in a method of fabricating an emitter area and collector area of a bipolar transistor, said emitter and collector being each covered with a portion of an oxidation mask layer, said improvement comprising the steps of:

• implanting ions of the conductivity type of said base region;
• forming an oxide stripe by thermal oxidation surrounding said emitter area;
• selectively removing portions of said oxidation mask layer;
• depositing successive layers comprising at least of a top layer and an underlying doped silicide layer;
• anisotropically etching through said oxide stripe used as a mask to form successive layers divided into an emitter electrode and a collector electrode;
• and
• diffusing said emitter region and said collector contact region from said emitter electrode and collector electrode respectively.

An improvement in a method of making a monolithic integrated circuit, said circuit formed in a wafer-shaped semiconductor substrate having a field-oxide layer disposed thereon and comprising at least one bipolar planar transistor having a collector, emitter and base region, said collector region lying at a main surface of said wafer-shaped semiconductor substrate and forming a collector area at said exposed surface within an opening of said field-oxide layer, wherein, to form said emitter region and said base region, said emitter area is covered with a portion of an oxidation mask layer of such a thickness that said oxidation mask layer is penetrated by dopants of said base region in a high-energy ion-implantation process and masked against dopants of said base region in a low-energy ion-implantation process, after said ion-implantation processes, which are carried out using an implantation mask defining said base area, said exposed semiconductor surface is thermally oxidized to form an oxide stripe surrounding said emitter area, whereafter said portion of said oxidation mask layer is removed, said improvement comprising the steps of:

• removing that portion of said oxidation mask layer covering said emitter area;
• providing said main surface of said semiconductor substrate with successive layers of at least an insulating top layer and an underlying silicide layer;
• dividing said oxide stripe into an inner portion and an outer portion using an anisotropic etching technique to form a moat through said successive layers, which comprise said top layer, and said silicide layer and to expose that portion of a PN junction between said outer base-region portion and said collector region which extends to said semiconductor surface, whereby in addition to said emitter electrode, said collector electrode is defined, which overlaps said field-oxide layer;
• implanting ions of said conductivity type of said base region with said successive layers acting as a mask;
• depositing an insulating layer to cover said surface of said moat and said remaining portions of said top layer;
• anisotropically etching in a gas phase, so that said rims of said moat, said rim of said emitter electrode, and said rim of said collector electrode remain covered by remaiders of said insulating layer;
• activating said implanted ions of said conductivity type of said base region by diffusing said ions therein;
• depositing a contact layer of contacting said resulting base contact region;
• and
• forming said base electrode using a photolithographic etching process.

An improvement in a method of making a monolithic integrated circuit, said circuit formed in a wafer-shaped semiconductor substrate having a fieldoxide layer disposed thereon and comprising at least one active region, said exposed semiconductor surface being thermally oxidized to form an oxide layer within an active area, said improvement comprising the steps of:

• providing the surface of said semiconductor substrate with successive layers of at least an insulating top layer and an underlying silicide layer;
• dividing said oxide layer into an inner portion and an outer portion using an anisotropic etching technique to form a moat through said sucessive layers, which comprise said top player, and said silicide layer and to expose that portion of a junction defining the outer boundary of said active region, which junction extends to the semiconductor surface;
• implanting ions of said conductivity type of said active region with said successive layers acting as a mask;
• depositing an insulating layer to cover said surface of said moat and said remaining portions of said top layer;
• anistropically etching in a gas phase, so that said rims of said moat remains covered by remainders of said insulating layer;
• activating said implanted ions of said conductivity type of said active region by diffusing said ions therein;
• depositing a contact layer for contacting said resulting active contact region;
• and
• forming said active electrode using a photolithographic etching process.