Processor to peripheral interface for asynchronous or synchronous applications

An interface between a peripheral and a system comprising:

• means for inverting a chip select signal and a data strobe signal and for ANDing the inverted signals to form a combined signal at a first output;
• means coupled to said first output for synchronizing the combined signal to a peripheral clock signal to form a synchronized signal and for reducing the possibility that metastable states will occur and for presenting said synchronized signal at a second output;
• means coupled to said second output for converting said synchronized signal to an instruction enable signal and for presenting said instruction enable signal at a third output;
• multiplexer means having a first input coupled to said third output and having a second input coupled to said first output and having a select input for receiving a control signal which has at least two states indicating whether the peripheral is coupled to a synchronous or an asynchronous system and having an instruction enable output at which appears said instruction enable signal representing the signal at either said first input or said second input of said multiplexer means depending upon the state of said control signal;
• an instruction bus input;
• and
• means for ANDing a signal from said instruction bus input of said peripheral with the signal at said first input of said multiplexer to form a second control signal and for using said second signal as a read write signal.