Intermittent receiver

An intermittent receiver comprising:

• a shift register including a plurality of cascaded flipflops and having a serial data input, a serial data output, a plurality of parallel data outputs and a clock input;
• a time signal generator including a decoder, connected at its inputs at least a portion of the parallel data outputs of the shift register so as to generate a time signal and a first gate means receiving at least a portion of the parallel outputs of the shift register so as to generate a feedback signal;
• a first selection circuit having one output connected to the serial data input of the shift register and a first input connected to an output of the first gate means and a second input connected to receive a reception signal;
• a second selection circuit having an output connected to the clock input of the shift register and a pair of inputs connected to receive a pair of different clocks, respectively;
• a delayed detector including a second gate means having a first input connected to the serial data output of the shift register and a second input connected to receive the reception signal so as to generate a detection signal;
• and
• control means receiving the time signal outputted from the decoder for controlling the conditions of the first and second selection circuits in such a manner that, when the time signal is indicative of a wait mode, the second selection means outputs one of the clock signals to the shift register and the first selection means outputs the feedback signal to the shift register so that the time signal generator generates a predetermined time signal, and when the time signal is brought into a condition indicative of a reception mode, the second selection means outputs the other clock signals to the shift register and the first selection means outputs the reception signal to the shift register so that delayed detector operates to execute the delayed detection for the reception signal.