Encoder/decoder circuit for B8ZS and B6ZS applications

A circuit for encoding B8ZS and B6ZS line codes comprising:

• data input means for receiving bytes of input data;
• means for deriving a rate selection control signal;
• shift register means for receiving said input data bytes for temporary storage;
• means for detecting a predetermined logic condition in said input data;
• and
• means responsive to said detected predetermined logic condition for encoding said temporarily stored data by substituting a code pattern for the temporarily stored input data, such that said code pattern substitution is made when six logic zeros are detected in said stored data when said rate selection control signal is at a logic level indicative of B6ZS line code, and said code pattern substitution is made when eight zeros are detected in said stored data when said rate selection control signal said at a logic level indicative of B8ZS line code.

A method for decoding B8ZS and B6ZS line codes comprising the steps of:

• receiving both B8ZDS and B6ZS input data, said input data including common line code pattern bits;
• decoding a rate control input signal to generate an output representative of whether said input data is B8ZS line code or B6ZS line code;
• temporarily storing said received input data;
• additional decoding logic means for decoding the last five bits of each data byte to decode said common line code pattern bits in each of the B8ZS and B6ZS line codes;
• decoding the number of logic zeros preceding said last five bits of each data byte in accordance with said control input signal;
• and
• substituting either eight logic zeros for a detected B8ZS code or six logic zeros for a detected B6ZS code in accordance with the decoding by said additional decoding logic means.

A method for encoding B8ZS and B6ZS line codes comprising:

• receiving bytes of input data;
• deriving a rate selection control signal;
• receiving said input data bytes for temporary storage;
• detecting a predetermined logic condition in said detected input data;
• and
• encoding said temporaily stored data by substituting a code pattern for the temporarily stored input data, such that said code pattern substitution is made when six logic zeros are detected in said stored data when said rate selection control signal is at a logic level indicative of B6ZS line code, and said code pattern substitution is made when eight logic zeros are detected in said stored data such that said rate selection control signal is at a logic level indicative of B8ZS line code.