Circuit arrangement for serial data transmission between a plurality of subscriber stations

In a circuit arrangement for the serial data transmission between first and second subscriber stations connected to a respective first and second transmission/receiving device and each of said subscriber stations including a data transmitter and a data receiver, each data transmitter and each data receiver connected to two leads of a data bus via a respective transmission/receiving device, each of said transmitters including a signal input, a control input responsive to control signals such that only one of the transmitters is active at a time to output to the data bus a voltage of a first polarity or of a second polarity dependent on the state of a data signal applied to its signal input by the respective transmission/receiving device, each of the transmitters having a higher internal impedance in the passive condition than in the active condition, and each of the receivers operable in response to the polarity of the voltage on its input received from the data bus to output data to the respective transmission/receiving device, the improvement therein comprising:

• a recognition circuit connected between the two leads of the data bus and the respective transmitter and receiver and operable to output a free signal having a first logic state given approximately identical voltages on the leads of the data bus and output a busy signal having a second logic state given different voltages on the leads of the data bus.