Normalizing circuit
AssigneeNEC Corporation
InventorsToshiya Takahashi, Junichi Iwasaki
Life of this patent
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Abstract
A normalizing circuit is disclosed which can make bit shift operation for a bit string. The normalizing circuit has a leading "one" detector, an encoder and a bit shifter. The leading "one" detector detects a bit position of a leading "one" among a bit string and produces a signal to indicate the bit position of the leading "one". The encoder produces a control signal by which bit shift operation is executed. The bit shifter has a plurality of shift paths to shift leftwardly or rightwardly the bit string such that the leading "one" bit is positioned at the most left position or the most right position. One of the plurality of shift paths is selected by the control signal produced by the encoder. Thus, bit shift operation of the leading "one" bit can be executed at a high speed.
Claims16
A leading "one" detector, connected to a source of a transmission signal of a first level, for detecting the position of a leading "one" in a bit string, comprising:
- a plurality of logic circuits connected in series, to each of which a respective bit of the bit string is applied as a first input,
- the first of said logic circuits receiving at a second input said transmission signal of said first level from said source and generating an output transmission signal, each other logic circuit in said series receiving, as a second input, an output transmission signal from a preceding logic circuit, all said logic circuits including a first output, each of said logic circuits except the last one further including a second output and generating at said second output an output transmission signal, each of said logic circuits except the last one having means for transferring the input transmission signal at its second input to its second output as its output transmission signal when the bit applied to its first input is not "one" and, inhibiting transmission of the input transmission signal at its second input to its second output and generating an output transmission signal of a second level different from said first level at its second output when the bit applied to its first input is "one", whereby said transmission signal of said first level from said source is transmitted to the second input of the logic circuit to which the leading "one" bit is applied and the input transmission signal at the second input of the less significant logic circuit with respect to said leading "one" logic circuit becomes of said second level.
A normalizing circuit for shifting a bit string consisting of a plurality of binary bits and comprising a leading "one" detector for detecting a bit position of a leading "one" in said bit string and for generating a signal indicating the bit position of said leading "one" bit, means coupled to said leading "one" detector for producing a data representing a number of bits to be shifted in response to the signal generated by said leading "one" detector, and a shifter coupled to said producing means and shifting said bit string to an extent designated by said data;
- said leading "one" detector including a plurality of logic circuits, each of said logic circuits receiving a respective bit of said bit string at a first input end and an input transmission signal at a second input end and producing an output signal at a first output end when a leading "one" signal is applied, each of said logic circuits except one receiving the least significant bit of said bit string generating an output transmission signal at a second output end, the output transmission signal of one logic circuit being applied to the second input end of the succeeding logic circuit as the input transmission signal thereto, the logic circuit to which the leading "one" bit is applied and its succeeding logic circuit or circuits generating a first level of output transmission signal at said second output end, the other logic circuit or circuits generating a second level of output transmission signal at said second output end, said first level being different from said second level, whereby only that logic circuit which receives the leading "one" bit and the transmission signal having said first level generates an output signal at said first output end as said signal indicating the bit position of said leading "one" bit.
A leading "one" detector for detecting the position of a leading "one" bit of a bit string, comprising a plurality of logic circuits arranged in serial and means for generating a transmission signal with a first level, each of the logic circuits having a first input end and receiving a respective bit of the bit string, a second input end, a first output end, a second output end, a first circuit coupled to said first and second input ends and said second output end, and a second circuit coupled to said first and second input ends and said first output end, a first means for coupling said generating means to the second input end of a first logic circuit of said plurality of logic circuits, a second means for coupling the second output end of a preceding logic circuit to the second input end of a succeeding logic circuit, the first circuit of each logic circuit having a switching means which is turned on to electrically couple the second input end to the second output end when a logic "zero" bit is applied at the first input end and is turned off to stop the transfer of a transmission signal with the first level to a succeeding logic circuit or circuits when a logic "one" bit is applied at the first input end, the second circuit of each logic circuit producing an output signal only when both the logic "one" bit and the transmission signal with the first level are applied at said first and second input ends, respectively, the output signal indicating the position of the leading "one" bit and being derived from the first output end.
A normalizing circuit for shifting a bit string consisting of a plurality of binary bits and comprising a leading "one" detector for detecting a bit position of a leading "one" in said bit string and for generating a signal indicating the bit position of said leading "one" bit, means coupled to said leading "one" detector for producing a data representing a number of bits to be shifted in response to the signal generated by said leading "one" detector, and a shifter coupled to said producing means and shifting said bit string to an extent designated by said data;
- said leading "one" detector including a generating means for generating a transmission signal with a first level, a plurality of logic circuits, each of which has an input circuit for receiving a respective bit of said bit string, a gate circuit and a logic circuit, and means for coupling said generating means and all of the gate circuits of the logic circuits in serial, said gate circuit further coupled to said input circuit and being turned on when a logic "zero" bit is received at said input circuit and turned off when a logic "one" bit is received at the input circuit, said logic circuit having its one input end coupled to an input end of the gate circuit and the other input end coupled to the input circuit and generating said signal when the logic "one" bit and the transmission signal with the first level are applied thereto.
A leading "one" detector for detecting the position of a leading "one" bit in a bit string, comprising:
- means for generating a transmission signal of a first level;
- a plurality of logic circuits arranged in series to each of which a respective bit of the bit string is applied, each of the logic circuits except one receiving the least significant bit of said bit string having first and second input ends and first and second output ends, transfer gate means coupled between said second input end and said second output end, switch means coupled between said second output end and a source of a second potential different from said first potential, an AND gate having first and second input terminals coupled to said first and second input ends, respectively, and an output terminal coupled to said first output end, first control means coupled to said first input end for enabling said transfer gate means when said first input end receives a logic "zero" bit and second control means for enabling said switching means when said first input end receives a logic "one" bit;
- means for applying said transmission signal to the second input end of a first logic circuit of said plurality of logic circuits, the second output end of one logic circuit being coupled to the second input end of its succeeding logic circuit, and means applying the respective bits in said bit string to the first input ends of the respective logic circuits, whereby the logic circuit receiving the leading "one" bit and the transmission signal generates at the first output end an output signal indicating the location of the leading "one" bit.
A leading "one" detector for detecting the position of a leading "one" bit in a bit string, comprising:
- a plurality of logic circuits arranged in series to each of which a respective bit of the bit string is applied, each of the logic circuits having first and second input ends, first and second output ends, a transfer gate coupled between the second input end and the second output end, a switch element coupled between the second input end and a source of a first potential, a NOR gate having a first input terminal coupled to the second input end and a second input end, an inverter having an input terminal coupled to the first input end and an output terminal coupled to the second input terminal of the NOR gate, first control means for enabling the transfer gate when the first input end receives a logic "zero" bit and second control means for operatively enabling the switch element;
- means for generating a transmission signal of a second level different from the first level;
- means applying said transmission signal to the second input end of a first logic circuit of said plurality of logic circuits;
- means for connecting the second output end of one logic circuit to the second input end of its succeeding logic circuit;
- and
- means for applying the respective bit of said bit string to the first input ends of the respective logic circuits.
Dependencies are inferred from the claim text.