US 4,785,416 AGranted

Microprocessor timing emulator having a "Wait" state

OwnerPhilip J. Stringerinventor

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Abstract

Within a test system for testing microprocessor-based systems, an apparatus for emulating the timing characteristics of a microprocessor, including when the microprocessor goes to a "WAIT" state during the execution of an instruction cycle. A control signal RAM has a plurality of sets of instructions, each set being stored in a specific region, each set corresponding to the timing characteristics, that is the control, address and data signals, of a microprocessor. A decode RAM stores coded instructions for addressing each region of the control signal RAM. A sequence control RAM contains data for addressing each address location in the region of the control signal RAM selected by a signal input to the decode RAM. In response to the combination of a clock signal and an external ready input signal, a sequence control latch supplies address signals to the control signal RAM to access a particular instruction of the selected instruction set and supplies the same signals to the address inputs of the sequence control memory. The sequence control memory then latches the address signals for the next instruction in the sequence control latch. The control signal memory stores data for producing a "WAIT" output. A change in the external ready input signal suspends the instruction address sequencing and causes the control signal memory to produce the "WAIT" output.

Claims16

Dependent claims

Apparatus for emulating the timing characteristics of a microprocessor, the apparatus comprising:

(a) a control signal memory storing data representing a plurality of sets of instructions, each instruction set being stored in a respective region of the said control signal memory and each instruction set comprising a plurality of instructions;
(b) a decode memory for receiving a signal specifying a given instruction set to be used for emulating the timing characteristics of a selected microprocessor and for supplying, in response to the instruction set specifying signal, first address signals to the control signal memory to select the region of the control signal memory storing the given instruction set;
(c) a sequence control memory for supplying, in response to the instruction set specifying signal, second address signals to select one instruction in the given instruction set;
(d) a sequence control latch for supplying the second address signals to the control signal memory;
and
(e) means for supplying a clock signal to the sequence control latch to actuate the sequence control latch to supply the second address signals to the control signal memory,
wherein the control signal memory stores data for producing a WAIT output and wherein the sequence control latch supplies the second address signals to the control signal memory only in response to an external ready input signal, and wherein a change in the ready input signal suspends the supplying of the second address signals by the sequence control latch and causes the control signal memory to produce the WAIT output, so that, in use, the instructions of the instruction set are supplied to emulate the timing characteristics of a microprocessor in a sequence determined by the sequence control memory.

4 more elements

Dependencies are inferred from the claim text.