US 4,785,415 AGranted

Digital data buffer and variable shift register

AssigneeHewlett-Packard Company

InventorRichard K. Karlquist

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Abstract

A combination FIFO buffer and programmable shift register having asynchronous input and output capabilities comprises a three stage system which synchronizes the incoming data stream with the memory input clock, buffers the incoming data stream and provides a variable delay for the data. The digital data stream from an input device is received by an input synchronizer having its input clocked at the clock rate of the input device clock and its output clocked at a higher internal clock rate. The data is written into two FIFO buffers, a master and a slave. The master buffer controls the read and write addresses of both buffers, so that the write address of the buffers advances only when valid data is written into the buffers, and the read address advances only when data is read out of the buffers. The slave buffer can be programmed with an offset in its read address, so it operates as a delay buffer. The data is read out of the buffers into an output synchronizer, having its input clocked at the internal clock rate its output clocked at the clock rate of the memory control.

Claims8

Dependent claims

A synchronous FIFO buffer memory for converting a variable rate input digital data stream clocked by an external input clock to an output digital data stream synchronized with an external output clock from a downstream device, wherein the external input clock and the external output clock are not synchronized with each other, comprising:

means for producing an internal clock signal with a frequency at least as high as the external clock frequencies, not synchronous with the input clock and the output clock;
an internal data bus;
an input synchronizer for receiving the input digital data stream and producing an output data stream on the internal data bus synchronized to the internal clock signal, said input synchronizer including a logic network that prevents the loss of data and violation of the setup and hold timing of the internal system clock upon occurrence of a metastable state caused by asynchronicity of the input clock and the internal clock;
a first FIFO memory connected to the internal data bus for receiving a first portion of the input digital data stream and temporarily holding the data until the downstream device is ready to receive the data;
a second FIFO memory connected to the internal data bus for receiving a second portion of the input digital data stream, reading data and writing data coincidentally with the first FIFO memory, and temporarily delaying a programmable number of data words, so that the second portion of the input digital data stream is delayed with respect to the first portion of the input digital data stream;
and
an output synchronizer connected to the internal data bus for receiving the data read from the first and second FIFO memories and producing an output digital data stream on an output bus connected to the downstream device, synchronized to the clock of the external downstream device.

4 more elements

Dependencies are inferred from the claim text.