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AssigneeMotorola, Inc.
InventorsCharles D. Thompson, Joseph P. Gergen, Bradley Martin, Garth D. Hillman
Estimating the term…
A filter structure uses multiple discrete filter circuits which are cascaded to provide a multiple tap filter of programmable tap length. In one form, an FIR filter may be implemented wherein each circuit generates partial sum operands which must be added to provide a filter output. The cascaded circuits perform partial addition operations near simultaneously by using a serial addition which is synchronized with a start bit. The number of taps in the filter structure implemented by the cascaded discrete filter circuits is variable and may be programmed with a programmable storage register in each discrete circuit which stores operand data fixing the tap length of each discrete circuit. The multiple filter circuits provide a single filter structure with a large tap length and high sampling rate.
A cascade filter structure having a plurality of rank ordered filter circuits, each of said filter circuits performing predetermined arithmetic calculations on predetermined operands to provide one of a plurality of rank ordered output operands, said rank ordered output operands being serially added by each rank ordered filter circuit except the lowest ranked filter circuit by an interface circuit in each filter circuit, each of said interface circuits comprising:
A cascade filter structure having a plurality of discrete rank ordered circuits, each of the circuits executing predetermined filter algorithms and providing a rank ordered partial addend, each rank ordered partial addend except the lowest ranked partial addend being added with a rank ordered partial addend of immediately lower rank by a corresponding ranked one of a plurality of rank ordered interface portions to provide a rank ordered output operand, the highest rank ordered circuit providing a filter output, the lowest rank ordered of said interface portions providing a start bit during a first cycle of predetermined length followed by the lowest rank ordered partial addend of predetermined bit length at one bit per cycle, said remaining rank ordered circuits receiving the start bit in succession one cycle later for each successively higher ranked circuit and adding respective rank ordered partial addends concurrently to provide the filter output within a number of cycles after the lowest ranked output operand is provided equal to the plurality of rank ordered circuits.
In a cascade filter structure having a plurality of discrete filter circuits performing predetermined arithmetic calculations on predetermined operands, wherein the improvement comprises:
Dependencies are inferred from the claim text.