Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page

A cache memory for use with a processing unit which connects to a main memory, said main memory being divided into a number of pages, each containing a plurality of blocks, each of which has a plurality of words, said cache memory providing fast access information fetched from said main memory in response to requests for information received from said processing unit, each request including an input address for identifying the information words to be accessed from said cache memory, said cache memory comprising:

• a plurality of content addressable memories, each having an input and an output and containing a plurality of locations for storing a first type of information pertaining to each of a number of said plurality of pages, a first one of said content addressable memories having said input coupled to receive said input address from said processing unit;
• a plurality of directly addressable random access memories, each having an input and an output and containing a plurality of locations for storing other types of information pertaining to each of said plurality of pages;
• a common internal bus connecting said output of said first one of said content addressable memories to said input of each of the remaining content addressable and each of said directly addressable memories in common;
• and,
• cache control means coupled to receive said requests from said processing unit, said cache control means being operative in response to each request for information to apply a first portion of said input address to said first one of said content addressable memories, said first content addressable memory being operative upon detecting a hit condition indicating that the page containing the requested information resides in cache memory to generate a page level number value on said bus identifying where said other types of information is stored in said content addressable and directly addressable memories associated with said pages, said cache control means applying said page level number value together with other portions of said input address as a cache address to other ones of said content addressable and random addressable memories for accessing the requested information words.

A method of organizing a cache memory for use with a processing unit which connects in common with other processing units to share a main memory, said main memory being divided into a number of pages, each containing a number of blocks each of which has a plurality of words, said cache memory providing fast access to information fetched from said main memory in response to requests from said processing unit, each request including an input address, said method comprising:

• (a) organizing each of a plurality of content addressable and directly addressable memories including a plurality of word locations into a plurality of levels;
• (b) storing in the word locations of each level in each memory, a different portion of all of the information pertinent to each page of a maximum number of pages which can be allocated space in said cache memory in response to requests from said processing unit;
• (c) connecting all of said memories to a common internal bus for enabling simultaneous access to all of said information of a page stored at the same level;
• (d) connecting only one of said content addressable memories between said processing unit and said common internal bus;
• and,
• (e) said one content addressable memory generating a page level number value in reponse to each request received from said processing unit upon detecting a comparison between said input address and the contents of one of said word locations for enabling access to all of said information stored in each of the remaining content addressable and directly addressable memories as required for processing said page.