US 4,785,341 AGranted

Interconnection of opposite conductivity type semiconductor regions

AssigneeInternational Business Machines Corporation

InventorsTak H. Ning, Siegfried K. Wiedmann

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Abstract

A technique for making ohmic electrical interconnections between semiconductor regions of opposite conductivity type, without requiring metallic interconnection lines. This technique has applicability in any circuit using bipolar devices, and in particular is useful to provide a very dense static memory array of bipolar transistors. To join the opposite conductivity regions, intermediate layers are formed including a silicide of a refractory metal, such as W, Mo, Ta, etc. and at least one layer of doped polycrystalline semiconductor material. For a single crystal of silicon having N and P type regions, the refractory metal silicide forms an electrical connection to at least one doped polysilicon layer of a first conductivity type and to either a single crystal semiconductor region of the opposite conductivity type or to another polysilicon layer which also has the opposite conductivity type. As an example, an N type silicon region is interconnected to a P type silicon region by intermediate layers of N polysilicon--refractory metal silicide--P polysilicon.

Claims2

Dependent claims

A semiconductor memory circuit, comprising:

a body of silicon single crystal semiconductor material having at least two cross-coupled bipolar transistors formed in a memory cell therein, wherein each of said transistors includes electrical base, collector, and emitter regions, said transistors being arranged in an improved dense layout, said layout including
a sufficiently low voltage drop electrical interconnection forming said cross-coupling between an electrical base region of one transistor and an electrical collector region of the second transistor, said cross-coupling interconnection comprising:
a refractory metal silicide layer contacting one of said base or collector regions in one of said first and second transistors and forming an electrical contact therewith, and
a polycrystalline silicon layer in contact with the other of said base or collector regions in the other of said first and second-transistors and sufficiently doped to form a sufficiently low voltage drop electrical contact therewith, said polycrystalline layer also being in contact with said layer of refractory metal silicide and forming a multi-level sandwich structure,
an electrical insulation layer formed over said silicide layer and said polycrystalline silicon layer,
a first electrical conductor located on said insulation layer and extending over the area in which said electrical interconnection is formed,
at least one additional electrical conductor formed in the same fabrication level as said first conductor and located laterally outside of the area occupied by said interconnection,
additional bipolar transistors electrically connected to said first conductor and said additional conductor, and to said two bipolar transistors, said additional bipolar transistors being located in said semiconductor material and between said two bipolar transistors.

5 more elements

A semiconductor memory circuit comprising a body of single crystal semiconductor material having two cross-coupled bipolar transistors formed in a memory cell therein

wherein each said bipolar transistor includes electrical base, collector, and emitter regions,
an electrical interconnection coupling said two transistors and forming said cross coupling between an electrical base region of one transistor and an electrical collector region of the second transistor, said cross-coupling electrical interconnection being comprised of:
a first polysilicon layer of a first conductivity-type being in contact with said base region of one transistor, the doping level of said first polysilicon layer being sufficiently high that a sufficiently low voltage drop electrical contact is formed to said base region,
a refractory metal silicide layer in contact with said first polysilicon layer, and
a second polysilicon layer of opposite conductivity-type in contact with said collector region of said second transistor and having a sufficiently high doping level to provide a sufficiently low voltage drop contact to said collector region, said second polysilicon layer also being in contact with said refractory metal silicide layer, where said silicide layer is located between said first and second polysilicon layers in a multilayer sandwich structure,
a layer of oxide insulation on said polysilicon layers, a first electrical conductor located over said oxide insulation and extending over the area in which said first and second polysilicon layers form said electrical interconnection to said base and collector regions,
at least one additional electrical conductor formed in the same fabrication level as said first conductor and located laterally outside the area occupied by said first conductor,
an additional bipolar transistor electrically connected to at least one of said first conductor and said additional conductor, and to at least one of said two bipolar transistors, said additional bipolar transistor being located in said semiconductor material and between said two bipolar transistors.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/136,480Filed 24 Dec 1987 · continuation
Priority: 29 Jun 1979
Granted: 15 Nov 1988
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 20/066
By modifying the conductivity of conductive parts, e.g. by alloying: by forming silicides of refractory metals
H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs
H10W 20/4451
Conductive materials thereof: semiconductor materials, e.g. polysilicon
Y10S 257/903
Active solid-state devices, e.g. transistors, solid-state diodes: fET configuration adapted for use as static memory cell