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US 4,785,259 AGranted
BIMOS memory sense amplifier system
AssigneeMotorola, Inc.
InventorsWalter C. Seelbach, Kevin L. McLaughlin, Danny J. Molezion
Life of this patent
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Abstract
A BIMOS amplifier having feedback clamping the amplifier's input to a predetermined voltage, minimizes input signal voltage excursions in the presence of large load capacitances. A pair of differentially coupled NPN transistors in response to first and second inputs drive a pair of emitter follower NPN transistors. First and second MOS transistors responsive to first and second enable signals are coupled between the ouptut from each of the emitters of the emitter follower transistors and the first and second inputs, respectively.
Claims16
A circuit comprising:
- a first supply voltage terminal;
- a second supply voltage terminal;
- a first input terminal;
- a second input terminal;
- a first enable terminal;
- a second enable terminal;
- a first output terminal;
- a second output terminal;
- first means coupled between said first and second supply voltage terminals and coupled to said first and second input terminals for differentially providing first and second signals;
- second means coupled between said first supply voltage terminal and said first output terminal and coupled to said first means and responsive to said first signal for providing a first output;
- third means coupled between said first supply voltage terminal and said second output terminal and coupled to said first means and responsive to said second signal for providing a second output;
- fourth means coupled between said first output terminal and said first input terminal and coupled to said first enable terminal for selectively clamping said input terminal;
- and
- fifth means coupled between said second output terminal and said second input terminal and coupled to said second enable terminal for selectively clamping said input terminal.
11 more elements
A memory circuit comprising:
- a plurality of word lines;
- a plurality of pairs of bit lines;
- a plurality of memory cells, wherein each of said memory cells are uniquely coupled between one of said pair of bit lines and to one of said plurality of word lines, each of said memory cells having a read mode and a write mode;
- first means coupled to said plurality of word lines for selecting one of said word lines;
- second means coupled to said plurality of pairs of bit lines for selecting one of said pair of bit lines;
- and
- a plurality of third means, each of said third means coupled to a pair of bit lines for sensing the voltage on said pair of bit lines for determining the mode of said memory cell uniquely coupled thereto, each of said third means comprising:
- a first output terminal;
- a second output terminal;
- fourth means coupled to said pair of bit lines for differentially providing first and second signals;
- fifth means coupled between said first means and said first output terminal and responsive to said first signal for providing a first output;
- sixth means coupled between said first means and said second output terminal and responsive to said second signal for providing a second output;
- seventh means coupled between one of said bit lines and said first output terminal for selectively clamping a voltage on said bit line during said read mode;
- and
- eighth means coupled between said another of said bit lines and said second output terminal for selectively clamping a voltage on said bit line during said read mode.
12 more elements
Dependencies are inferred from the claim text.