Digital FSK signal demodulator
AssigneeAllen-Bradley Company, Inc.
InventorsMark Lucak, Michael Klein
Life of this patent
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Abstract
A demodulator for a phase coherent frequency shift keyed signal has a master clock which generates a signal having a plurality of pulses during each half of the bit internal of the FSK signal. A detector determines during which master clock pulse within several groups of X number of pulses the most transitions occur in the received signal. Based on the determined clock pulse, samples taken in each of two consecutive half-bit intervals of the FSK signal are selected for comparison to produce the demodulator output signal.
Claims14
A demodulator for a frequency shift keyed (FSK) signal having bit intervals during each of which a bit of data is transmitted, the demodulator comprising:
- means for generating a master clock signal having X number of pulses during each half of the bit interval of the FSK signal;
- means for sampling the FSK signal during each pulse;
- means for counting the number of transitions in the FSK signal that correspond in time to each of the same ordinally numbered pulses in a plurality of groups of X ordinally numbered pulses,
- means for indicating for which ordinally numbered pulse the most transitions were counted;
- and
- means responsive to the indicating means for comparing a pair of samples selected from different halves of a bit interval.
A demodulator for a frequency shift keyed signal having intervals during each of which a bit of data is transmitted, the demodulator comprising:
- means for sampling the FSK signal Y number of times during each bit interval;
- means for detecting signal transitions between samples in a group of X ordinally numbered samples, where X is less than Y;
- means for determining for which one of the same ordinally numbered samples of several groups of samples the most transitions occur;
- and
- means responsive to said determining means for selecting the signal samples to be used for signal decoding.
A demodulator for a frequency shift keyed signal having bit intervals during each of which a bit of data is transmitted, the demodulator comprising:
- means for generating a clock signal having Y number of cycles per bit interval;
- means for producing X number of different secondary clock signals, each having a frequency that is one-half the frequency of the clock signal;
- a first flip-flop having an input for receiving the frequency shift keyed signal, a clock terminal coupled to said clock signal generating means, and an output terminal;
- a second flip-flop having an input connected to the output terminal of the first flip-flop, a clock terminal coupled to said clock signal generating means, and an output terminal;
- a first comparator means connected to the output terminals of the first and second flip-flops for producing a signal indicating the comparison of the outputs of the two flip-flops;
- a first set of X flip-flops each having an input terminal connected to the comparator means for receiving the indicating signal, each flip-flop in the first set having a clock input terminal which receives a different secondary clock signal;
- a set of X counter circuits, each one connected to the output of a different flip-flop in the first set and each counter circuit having an enable terminal which receives a different secondary clock signal;
- means for determining which one of the X counter circuits has the greatest count;
- a second set of X flip-flops, each having an input terminal connected to the output of the first flip-flop, and each having a clock terminal which receives a different secondary clock signal;
- a third set of X flip-flops, each of which having an input terminal connected to the output of a different one of the flip-flops in the second set, and each having a clock terminal which receives the same secondary clock signal as the flip-flop in the second set to which the flip-flop in the third set is connected;
- a set of X second comparator means each of which is connected to the output of a flip-flop in the second set and the output of a flip-flop in the third set;
- and
- means responsive to the determining means for selecting the output from one of the X second comparator means.
Dependencies are inferred from the claim text.