High speed ECL to CMOS converter
AssigneeNCR Corporation
InventorsIkuo J. Sanwo, Mukesh B. Suthar
Life of this patent
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Abstract
An ECL to CMOS converter which connects the ECL input signal directly to the source electrode of a MOS gate, and the gate electrode of the MOS gate is independently regulated by connection to a reference voltage that is current sinked through a D.C. path to the negative CMOS voltage supply terminal. The drain electrode of the MOS gate is connected to the input of a CMOS inverter to provide the necessary logic level shift. Another MOS gate provides a D.C. signal path by connecting the input of the CMOS inverter to the negative CMOS voltage supply terminal.
Claims6
An ECL to CMOS converter for converting ECL logic level signals to CMOS logic level signals comprised of:
- a first MOS gate, of first conductivity type, having source, drain, and gate electrodes, the source electrode connected to receive ECL logic level signals;
- a second MOS gate, of first conductivity type, having source, drain, and gate electrodes, the drain electrode connected to the gate electrode, the source electrode connected to a biasing voltage, and the drain and gate electrodes further connected to the gate electrode of said first MOS gate;
- a first and a second power terminal having voltage levels thereat corresponding to high and low CMOS logic levels, respectively;
- a current sink connected between the drain and gate electrodes of said second MOS gate and said second power terminal;
- a third MOS gate, of second conductivity type, having source, drain, and gate electrodes, the drain electrode connected to the drain electrode of said first MOS gate, the source electrode connected to said second power terminal and the gate electrode connected to said first power terminal;
- and
- a complementary inverter circuit connected between said first and said second power terminals, said inverter circuit having an input connected to the drain of said first MOS gate, and an output for providing CMOS logic level signals in response to the ECL logic level signals at the source of said MOS gate.
Dependencies are inferred from the claim text.