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US 4,785,201 AGranted
High speed/high drive CMOS output buffer with inductive bounce suppression
AssigneeIntegrated Device Technology, Inc.
InventorMarcelo A. Martinez
Life of this patent
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Abstract
An output buffer is disclosed which employs a first pair of transistors connected in an (N-channel over P-channel) totem pole configuration, a second pair of transistors connected in a (P-channel over N-channel) totem pole configuration in parallel with the first pair of transistors, and a pair of inverters connected to delay the drive to the second pair of transistors.
Claims8
An output buffer comprising in combination:
- a line for connection to receive an externally developed power supply potential;
- a line upon which the output buffer develops a data output signal;
- coupling means for coupling said power supply potential line to said data output signal line;
- a line for connection to receive an externally developed circuit ground potential;
- a line for connection to receive an externally developed first data input signal;
- first delay means including a data input connected to said first data input signal line and a data output;
- an N-channel transistor including a gate connected to said first delay means data output, drain means connected to said data output signal line, and source means connected to said circuit ground potential line;
- and
- a P-channel transistor including a gate connected to said first delay means data input, source means connected to said data output signal line, and drain means connected to said circuit ground potential line.
6 more elements
Dependencies are inferred from the claim text.