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AssigneeAmerican Telephone and Telegraph Company, AT&T Bell Laboratories
InventorsTzu-Yin Chiu, Gen M. Chin, Ronald. C. Hanson, Maureen Y. Lau, Kwing F. Lee, Mark D. Morris, Alexander M. Voschenkov
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A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has a typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar device during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.
In a process for creating bipolar and CMOS transistors on a p-type silicon substrate where n+ buried wells have been implanted, a p-type epitaxial layer has been grown over the substrate, and field isolation regions have been created to isolate the CMOS and bipolar transistor regions on the wafer, said process comprising the following steps:
Dependencies are inferred from the claim text.