US 4,782,458 A · Architecture for power of two coefficient FIR filter

Abstract

An architecture for a very large scale integrated (VLSI) implementation of a finite imprise response (FIR) digital filter having no multipliers and a coefficient space limited to powers of two. The filter structure includes a data bus, a coefficient bus and a sum-in bus to each coefficient tap. Each tap has a coefficient and control word register which is loaded during an initialization phase of the filter. Multiplication is provided by a shifter which provides the correct power of two weighting of an input data sample. The weighted data sample at each tap is added to the output of the previous tap. This architecture results in a regular, modular structure which can be cascaded and which is programmable for various data word lengths and coefficient spaces.

Claims16

Dependent claims

A non-recursive finite impulse response (FIR) digital filter of n taps, where 1.ltoreq.n, comprising:

means to receive and store a plurality of coefficients, one coefficient per tap, wherein each coefficient is an integral power of 2;
means to receive and shift a data input word in each of said taps, the extent of said shift being determined by the value of the coefficient stored in said tap;
said shifted data word being equivalent to the product of said input data word and said coefficient of said tap;
means to add said product at each tap to the delayed output of the previous tap to thereby form at each tap the cumulative sum of the products at all previous taps;
means to delay and forward said cumulative sum to the next tap, and
means to output the cumlative sum of all taps in said filter.

3 more elements

Dependencies are inferred from the claim text.

Architecture for power of two coefficient FIR filter

Life of this patent

Architecture for power of two coefficient FIR filter

Life of this patent

Abstract

Claims16