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US 4,780,846 AGranted
Master slice type semiconductor circuit device
AssigneeFujitsu Limited
InventorsTomoaki Tanabe, Shigeru Fujii, Yoshihisa Takayama
Life of this patent
Estimating the term…
Abstract
A master slice type semiconductor circuit device including a memory block having at least one memory circuit; one conductive layer provided to peripheral portions of the memory circuit and used as an input portion thereto; power source lines provided to the peripheral portion of the memory circuit and formed by a conductive layer different from the conductive layer of the input portion; and a contact hole for connecting between the two conductive layers at a selected input portion. The selected input portion connected by the contact hole is set or clamped to a predetermined logic level by the power source line. This enables a change of the memory capacity or the function of the memory block to satisfy customer requirements.
Claims24
A master slice type semiconductor circuit device, comprising:
- at least one memory circuit block having a plurality of input circuits receiving an address signal and a peripheral portion;
- a plurality of fixed position input lines provided at the peripheral portion of said memory circuit block and connected to said input circuits respectively for receiving input signals, said input lines being formed in parallel in a first direction and of a first conductive layer;
- a first fixed position conductive line provided at the peripheral portion of said memory circuit block, extending in a second direction, intersecting each input line creating points of intersection, and for supplying a first voltage having a first logic level;
- a second fixed position conductive line provided extending in the second direction, intersecting each input line creating points of intersection and for supplying a second voltage having a second logic level, said first and second conductive lines being formed of a second conductive layer which is a different layer from said first conductive layer;
- and
- contact means, at the points of intersection, for connecting one of said first or second conductive lines to at least one of said input lines, the address signal being provided to the input lines not connected to said first or second conductive lines;
- wherein a potential of at least one of said input signals is clamped to one of said first and second logic levels by said contact means, thereby changing one of memory capacity and function of said memory block.
4 more elements
A gate array type large-scale integrated circuit master slice device, comprising:
- a logic block having a plurality of basic cells arranged in a grid and producing an address signal;
- a memory block having at least one memory circuit and peripheral portions;
- fixed position input terminals formed of a first conductive layer, provided at the peripheral portions of said memory circuit, extending parallel and in a first direction, and operatively connected to said memory block and said logic block;
- a pair of fixed position power source lines provided at said peripheral portions of said memory circuit extending in a second direction, intersecting said input terminals forming intersection points and formed of a second conductive layer different from said first conductive layer of said input terminals;
- and
- at least one contact hole located at one of the intersection points, connecting said first conductive layer and said second conductive layer at a selected one of the input terminals, said input terminals not connected to said power source lines receiving the address signal;
- wherein said selected input terminal connected by said contact hole is set to a predetermined logic level by a selected one of said power source lines, thereby changing one of memory capacity and function of said memory block.
4 more elements
A gate array type large-scale integrated circuit master slice device, comprising:
- a logic block having a plurality of basic cells arranged in a grid and producing an address signal;
- a memory block having at least one memory circuit and peripheral portions;
- an input basic cell row provided at said peripheral portions of said memory circuit at a layer of a basic cell, operatively connected to said memory block and said logic block and having input basic cells provided in parallel to a row direction and transferring the address signal to said memory block;
- fixed position power source lines provided at said peripheral portions of said memory circuit and formed of a first conductive layer above the basic cell level of said basic cell, extending in the row direction and intersecting each input basic cell in said input basic cell row producing intersection points;
- and
- at least one contact hole, located at one of said intersection points, for connecting one of said power source lines and a selected input basic cell, said input basic cells of said basic cell row not connected to said power source lines receiving the address signal;
- wherein said selected input basic cell connected by said contact hole is set to a predetermined logic level by the one of said power source lines, thereby changing one of memory capacity and function of said memory block.
4 more elements
A gate array type large-scale integrated circuit master slice device, comprising:
- a logic block having a plurality of basic cells and at least one stacked gate, the basic cells being arranged in a grid and producing an address signal;
- a memory block having at least one memory circuit;
- an input basic cell row including input basic cells provided in a row and parallel to a row direction, forming input circuits connecting said memory block and said logic block, and transferring the address signal;
- power source lines provided for said logic block and formed of first and second conductive layers of aluminum wiring intersecting said input basic cells forming intersection points;
- and
- at least one contact hole, located at one of the intersection points, for connecting between one of said power source lines and said stacked gate, said input basic cells not connected to said power source lines receiving the address signal from said logic block;
- wherein said stacked gate connected by said contact hole is set to a predetermined logic level by the one of said power source lines, thereby changing one of memory capacity and function of said memory block.
4 more elements
Dependencies are inferred from the claim text.