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US 4,780,843 AGranted
Wait mode power reduction system and method for data processor
AssigneeMotorola, Inc.
InventorDonald L. Tietjen
Life of this patent
Estimating the term…
Abstract
A method and apparatus for reducing power consumption in a data processing system by interrupting the supply of clocking pulses to selected portions of the system in response to a power-down signal provided by a data processing portion of the system only if the state of a respective control signal indicates that that particular portion of the system is then disabled or otherwise inhibited from interrupting the operation of the data processing portion.
Claims3
In a data processing system comprising:
- data processor means for executing instructions and for responding to interrupt requests;
- subsystem means for providing interrupt requests to said data processor;
- interrupt mask means responsive to the execution of instructions by said data processor means for preventing sid data processor means for responding to interrupt requests from said subsystem means;
- and
- clock means for supplying clocking pulses to said data processor means and said subsystem means;
- a power reduction system comprising:
- wait mode means responsive to a power-down signal received from said data processor means for reducing power consumption by the data processing system;
- and
- clock stopping means responsive to said power-down signal for interrupting the supply of clocking pulses to said subsystem means only if said interrupt mask means is preventing said data processor means from responding to interrupt requests from said subsystem means.
6 more elements
Dependencies are inferred from the claim text.