Cellular processor apparatus capable of performing floating point arithmetic operations

A processor apparatus for performing floating point arithmetic, by operating on at least first and second digital words each of a predetermined given number of bits with each word having a given number of slices each of a lesser number of bits than said word, with a first slice designated as a least significant slice (LSS) a second slice designated as an intermediate significant slice (ISS) and a third slice designated as a most significant slice (MSS), said processor apparatus including a plurality of individual processing cells of a number equal to said number of bits in said word and interconnected from left to right in a chain so that any of said processing cells can operate to receive any bit of any slice, wherein each of said cells comprises;

• memory means having first and second output ports each for transmitting an output bit of a digital word and having an input port for receiving a bit of a digital word and having means for storing said words, said first and second output ports and said input port being addressable;
• first multiplexer means, having an output coupled to said input port of said memory means and having a plurality of inputs, for selectively coupling any one of said inputs to said output when said one of said inputs is selected by a control signal applied to a control terminal of said first multiplexer means,
• arithmetic logic unit means, having a first input port coupled to said first output port of said memory means and a second input port coupled to said second output port of said memory means, for performing any one of a given number of arithmetic operations, said arithmetic logic unit means having an output port for providing a digital output indicative of the result of a performed operation, said output port of said arithmetic logic unit means coupled to a digital bus means having an output coupled to a first input of said first multiplexer means,
• controllable multiplier/quotient storage means having one input coupled to said digital bus means and an output coupled to a second input of said first multiplexer means, said multiplier/quotient storage means operative to store digital data indicative of an arithmetic operation, and having a control terminal for receiving a control signal for controlling the flow of data from said multiplier/quotient storage means,
• controllable loop path means having one input coupled to said digital bus means and one output coupled to a third input of said first multiplexer means and to an input of said controllable multiplier/quotient storage means, and having a control terminal for receiving a control signal for controlling the flow of data from said loop path means,
• controllable status path means having one input coupled to said digital bus means and an output coupled to a fourth input of said first multiplexer means and to an input of said controllable multiplier/quotient means and having a control terminal for receiving a control signal for controlling the flow of data from said status path means,
• control means coupled to said first multiplexer means, said arithmetic logic unit means, said multiplier/quotient storage means, said loop path means and said status path means for providing control signals thereto to enable any of said means to provide data at the output of said means in accordance with the control signal and in accordance with a given operation to be performed, whereby any bit stored in any of said means can serve as said first, second or third slice of said digital word.