Packages for hybrid integrated circuit high voltage isolation amplifiers and method of manufacture

A hybrid integrated circuit comprising in combination:

• (a) a ceramic substrate;
• (b) a first planar capacitor including first and second coplanar metal film conductors on the ceramic substrate each having a first portion closely and precisely spaced from and parallel to the other and having a predetermined capacitive coupling to the other;
• (c) a dielectric layer on the first parallel portions and on the substrate between the first parallel portions of the first and second metal film conductors, the dielectric layer including first and second openings exposing first and second areas, respectively, of the ceramic substrate and defining first and second cavities, respectively;
• (d) a first terminal of the first planar capacitor including an exposed portion of the first metal film conductor extending into the first cavity and a second terminal of the first planar capacitor including an exposed portion of the second metal film conductor extending into the second cavity, the first palnar capacitor forming a high voltage isolation barrier between the first and second terminals;
• (e) input integrated circuit chip means for producing a first pulse signal on the first terminal in response to an input signal, the first pulse signal being coupled across the isolation barrier to produce a second pulse signal to the second terminal;
• and
• (f) output integrated circuit chip means for producing an output signal in response to the second pulse signal on the second terminal, the dielectric layer being sufficiently thick that (1) the first cavity is deep enough to contain the input integrated circuit chip means and a bonding wire bonded at one end to a bonding pad on the input integrated circuit chip means and bonded at another end to the exposed portion of the first metal film conductor and (2) the second cavity is deep enough to contain the output integrated circuit chip means and a bonding wire bonded at one end to a bonding pad on the output integrated circuit chip means and bonded at another end to the exposed portion of the second metal film conductor.

A hybrid integrated circuit package comprising in combination:

• (a) a ceramic substrate;
• (b) first and second coplanar metal film conductors on the substrate, the first and second metal film conductors each having a closely, precisely spaced parallel portion and forming a planar first fringe capacitor;
• (c) a dielectric layer on the parallel portions and on the substrate between the parallel portions;
• (d) first and second openings in the dielectric layer exposing first and second areas, respectively, of the substrate, the first and second openings defining first and second cavities, respectively;
• and
• (e) an end portion of the first metal film conductor extending into the first cavity, an end portion of the second metal film conductor extending into the second cavity, the dielectric layer being sufficiently thick that the first and second cavities each are deep enough to contain an integrated cirucit chip and a wire bond including a piece of bonding wire having one end bonded to a bonding pad on the integrated circuit chip and another end bonded to the metal film end portion in that cavity when a flat cover is placed on the dielectric layer over that cavity.

A hybrid integrated circuit comprising in combination:

• (a) a ceramic substrate;
• (b) a first planar capacitor including first and second coplanar metal film conductors on the ceramic substrate each having a first portion closely and precisely spaced from and parallel to the other and having a predetermined capacitive coupling to the other;
• (c) a dielectric layer on the first parallel portions and on the substrate between the first parallel portions of the first and second metal film conductors;
• (d) a first terminal of the first planar capacitor including an exposed portion of the first metal film conductor extending beyond one side of the dielectric layer and a second terminal of the first planar capacitor including an exposed portion of the second metal film conductor extending beyond an opposite side of the dielectric layer, the first planar capacitor forming an isolation barrier between the first and second terminals;
• (e) input circuit means for producing a first pulse signal on the first terminal in response to an input signal, the first pulse signal being coupled across the isolation barrier to produce a second pulse signal on the second terminal;
• (f) output circuit means for producing an output signal in response to the second pulse signal on the second terminal;
• and
• (g) a toroidal transformer disposed on the dielectric layer and having a primary winding coupled to the output circuit and a secondary winding coupled to the input circuit, wherein the primary winding includes a plurality of elongated strips of thin film metal on the ceramic substrate adjacent to the output circuit means and a plurality of wire bond loops each wire bonded to and looping from one end of one of the elongated thin film metal stripes over an adjacent portion of the toroidal transformer to the opposite end of an adjacent thin film metal stripe and wire bonded thereto to form the primary winding of the toroidal transformer, and also includes a plurality of elongated thin film metal film stripes adjacent to the input circuit means, a plurality of wire bond loops each wire bonded to and looping from one end of one of those metal film stripes over an adjacent portion of the toroidal transformer to the opposite end of an adjacent thin film metal stripe and wire bonded thereto to form the secondary winding of the toroidal transformer, wherein the first capacitor is located beneath the region bounded by the toroidal core.