Back to results
US 4,779,220 AGranted
Floating-point data rounding and normalizing circuit
AssigneeNEC Corporation
InventorTomoji Nukiyama
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeNEC Corporation
InventorTomoji Nukiyama
Estimating the term…
A floating-point data rounding and normalizing circuit comprises a shift controller receiving a fraction portion of an input floating-point data for generating a shift control signal indicative of a shift amount required for normalization. A barrel shifter receives the fraction portion of the input floating-point data and is controlled by the shift control signal to shift the fraction portion by the required amount. A round circuit receives the shifted fraction portion for rounding it, and if an overflow occurs in the rounding operation by the rounding circuit, it is detected by a detector. A rounded fraction is inputted to another shifter controlled by the overflow detector so as to shift back the rounded fraction output one bit in response to generation of the overflow. Further, an encoder are provided to generate a two's complement of a binary number indicating the above mentioned required shift amount, and an addition circuit receiving an exponent portion of the input floating-point data, the two's complement and an output of the overflow detecting means for generating a normalized exponent data.
A floating-point data rounding and normalizing circuit comprising means receiving a fraction portion of an input floating-point data for generating a shift control signal indicative of a shift amount required for normalization, first shift means receiving the fraction portion of the input floating-point data and controlled by the shift control signal to shift the fraction portion by the required amount, means receiving the shifted fraction portion for rounding it, means for detecting an overflow in the rounding operation by the rounding means, second shift means receiving a rounded fraction output from the rounding means and controlled by the overflow detecting means so as to shift back the rounded fraction output one bit in response to generation of the overflow, means generating a two's complement of a binary number indicating the above mentioned required shift amount, and addition means receiving an exponent portion of the input floating-point data, the two's complement and an output of the overflow detecting means for generating a normalized exponent data.
Dependencies are inferred from the claim text.