Non-volatile semiconductor memory device

A non-volatile semiconductor memory device comprising:

• a semiconductor substrate of a first conductivity type;
• a impurity buried substrate of a second conductivity type different from said first conductivity type, formed at a surface of said semiconductor substrate, for constituting one of a drain region and a source region of a transistor;
• an epitaxial layer of said second conductivity type formed at a surface of said impurity buried layer;
• an insulating wall extending from a surface of said epitaxial layer to said impurity buried layer to form an independent vertical channel region as a part of said epitaxial layer;
• an impurity surface region of said second conductivity type, formed at a surface of said independent vertical channel region and constituting the other of said drain region and said source region of said transistor;
• a silicon oxide film formed on said independent vertical channel region;
• a silicon nitride layer formed in said insulating wall, which faces said independent vertical channel region on said silicon oxide film, said silicon oxide film of a thickness to cause an induced tunnel effect;
• and
• at least two control gate electrodes extending vertically in said insulating wall, separately facing said independent vertical channel region with said silicon nitride layer therebetween.

A non-volatile semiconductor memory device comprising:

• a semiconductor substrate of a first conductivity type;
• a impurity buried layer of a second conductivity type formed at a surface of said semiconductor substrate, different from said first conductivity type, for constituting one of a drain region and a source region of a transistor;
• an epitaxial layer of said second conductivity type formed at a surface of said impurity buried layer;
• an insulating wall extending from a surface of said epitaxial layer to said impurity buried layer to form an independent vertical channel region as a part of said epitaxial layer;
• an impurity surface region of said second conductivity type formed at a surface of said independent vertical channel region, constituting the other of said drain region and said source region of said transistor;
• a silicon oxide film formed on said independent vertical channel region;
• at least one electron accumulating region, facing said independent vertical channel region;
• a first insulation film between said electron accumulating region and said insulating walls, of a thickness to cause an induced tunnel effect;
• a second insulation film;
• and
• at least one control gate electrode extending vertically in said insulating wall, and facing said electron accumulating region with said second insulation film therebetween, and controlling a conductivity between said impurity buried layer and said impurity surface region.