Monolithic integration of silicon and gallium arsenide devices

A method of fabricating semiconductor devices of gallium arsenide and semiconductor devices of silicon on a common Si, SOS, or SOI substrate surface comprising the steps of:

• (a) forming a heavily doped connection region in said substrate;
• (b) forming silicon devices on selected regions of said surface adjacent said connection region with a portion of said silicon devices contacting said connection region;
• (c) forming a protective layer over said devices and adjacent regions of said substrate;
• (d) forming openings through said protective layer to expose additional regions of the surface of said substrate, said openings exposing at least a portion of said connection region;
• (e) forming a gallium arsenide buffer layer over the exposed surface regions;
• (f) forming a gallium arsenide semiconductor device over the buffer layer;
• and
• (g) forming ohmic contacts on said devices.

A method of fabricating compound semiconductor devices of III-V or II-VI material and semiconductor devices of silicon on a common substrate with low resistance interconnections between the compound semiconductor devices and the silicon devices comprising the steps of:

• (a) forming Si devices on selected areas of a planar surface of said substrate having junctions formed of opposite conductivity regions and wherein one of said regions extends laterally along the planar surface of the substrate;
• (b) forming a protective layer over the Si devices and portions of said substrate surface;
• (c) forming openings laterally displaced from the Si devices through said protective layer to expose regions of the surface of said substrate including at least a portion of said extended region;
• (d) forming a buffer layer of said compound semiconductor of the same type conductivity as the extended region over the protective layer and the exposed surface regions, which layer is single crystalline above the exposed surface regions and polycrystalline elsewhere;
• (e) removing the compound semiconductor polycrystalline layer to the extent deposited elsewhere;
• (f) forming said compound semiconductor devices on the remaining single crystalline compound semiconductor with said extended region of said Si devices forming said low resistance interconnection to said buffer layer;
• and
• (g) forming ohmic contacts on said devices.

A method of fabricating compound semiconductor devices of III-V or II-VI material and semiconductor devices of silicon on a common substrate comprising the steps of:

• (a) forming Si devices on selected areas of said substrate wherein said substrate comprises a single crystal wafer oriented at an angle of about 3.degree. off the (100) crystallographic plane toward the (111) plane;
• (b) forming a protective layer over the Si devices and the remainder of said substrate;
• (c) forming openings laterally displaced from the Si devices through said protective layer to expose regions of the surface of said substrate;
• (d) forming a layer of said compound semiconductor over the protective layer and the exposed surface regions, which layer is single crystalline above the exposed surface regions and polycrystalline elsewhere;
• (e) removing the compound semiconductor polycrystalline layer;
• (f) forming said compound semiconductor devices on the remaining single crystalline compound semiconductor;
• and
• (g) forming ohmic contacts on said devices.

A method of fabricating compound semiconductor devices of III-V or II-VI material and semiconductor devices of silicon on a common substrate comprising the steps of:

• (a) forming Si devices on selected areas of said substrate;
• (b) forming a protective layer over the Si devices and portions of the remainder of said subsrate laterally displaced therefrom;
• (c) forming openings laterally displaced from the Si devices through said protective layer to expose regions of the surface of said substrate;
• (d) forming a layer of said compound semiconductor over the protective layer and the exposed surface regions, which layer is single crystalline above the exposed surface regions and polycrystalline elsewhere;
• (e) removing the compound semiconductor polycrystalline layer;
• (f) forming said compound semiconductor devices on the remaining single crystalline compound semiconductor;
• and
• (g) then forming ohmic contacts on said devices.